XR17D154 Exar Corporation, XR17D154 Datasheet - Page 25

• Manufacturer Part Number: XR17D154
• Description: Four-channel Pci-bus Uart
• Manufacturer: Exar Corporation

XR17D154
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
REV. P1.0.0
Automatic RTS/DTR and CTS/DSR flow control, also known as hardware flow control, is used to prevent data
overrun to the local receiver FIFO and remote receiver FIFO. The RTS#/DTR# output pin is used to request
remote unit to suspend/restart data transmission while the CTS#/DSR# input pin is monitored to suspend/
restart local transmitter. The auto RTS/DTR and auto CTS/DSR flow control features are individually selected
to fit specific application requirement and enabled through EFR bit-6 and 7 and MCR bit-2 for either RTS/CTS
or DTR/DSR control signals. The auto RTS/DTR function must be started by asserting RTS/DTR# output pin
(MCR bit-0 or 1 to logic 1 after it is enabled.
Two interrupts associated with RTS/DTR and CTS/DSR flow control have been added to give indication when
RTS/DTR# pin or CTS/DSR# pin is de-asserted during operation. The RTS/DTR and CTS/DSR interrupts must
be first enabled by EFR bit-4, and then enabled individually by IER bit-6 and 7, and chosen with MCR bit-2.
Automatic hardware flow control is selected by setting bits 6 (RTS) and 7 (CTS) of the EFR register to logic 1.
If CTS# pin transitions from logic 0 to logic 1 indicting a flow control request, ISR bit-5 will be set to logic 1, (if
enabled via IER bit 6-7), and the UART will suspend TX transmissions as soon as the stop bit of the character
in process is shifted out. Transmission is resumed after the CTS# input returns to logic 0, indicating more data
may be sent.
O
5.2
UTPUT
MCR Bit-7=1
T
115.2k
230.4k
ABLE
19.2k
38.4k
57.6k
1200
2400
4800
9600
100
600
Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation
Data Rate
9: T
YPICAL DATA RATES WITH A
O
UTPUT
MCR Bit-7=0
153.6k
230.4k
460.8k
921.6k
19.2k
38.4k
76.8k
2400
4800
9600
400
Data Rate
Clock (Decimal)
D
IVISOR FOR
2304
14.7456 MH
384
192
96
48
24
12
6
4
2
1
Figure 11
16x
D
25
below explains how it works.
IVISOR FOR
Z CRYSTAL OR EXTERNAL CLOCK AT
Clock (HEX)
900
180
C0
0C
60
30
18
06
04
02
01
16x
DLM P
V
ALUE
09
01
00
00
00
00
00
00
00
00
00
ROGRAM
(HEX)
DLL P
V
ALUE
PRELIMINARY
C0
0C
00
80
60
30
18
06
04
02
01
16X S
ROGRAM
(HEX)
áç
áç
áç
áç
AMPLING
D
E
ATA
RROR
0
0
0
0
0
0
0
0
0
0
0
R
ATE
(%)