78Q2120C Teridian Semiconductor Corp. (TDK Semiconductor), 78Q2120C Datasheet - Page 11

• Manufacturer Part Number: 78Q2120C
• Description: 10/100 Ethernet PHYS
• Manufacturer: Teridian Semiconductor Corp. (TDK Semiconductor)

78Q2120C
10/100BASE-TX Transceiver
MR0: Control Register
© 2003 TDK Semiconductor Corporation, Proprietary and Confidential
0.15
0.14
0.13
0.12
0.11
0.10
Bit
0.9
SPEEDSL
ANEGEN
LOOPBK
PWRDN
Symbol
RANEG
RESET
ISO
Type
R/SC
R/SC
R/W
R/W
R/W
R/W
R/W
Default Description
(1)
(1)
(0)
0
0
0
0
Reset: Setting this bit to ‘1’ resets the device and sets all registers to
their default states. This bit is self-clearing.
Loopback: When this bit is set to ‘1’, no transmission of data on the
network medium occurs and any receive data on the network medium
is ignored. By default, the loopback signal path will encompass as
much of the 78Q2120C circuitry as possible.
Speed Selection: This bit determines the speed of operation of the
78Q2120C. Setting this bit to ‘1’ indicates 100Base-TX operation and
a ‘0’ indicates 10Base-T mode. This bit will default to a ‘1’ upon reset.
If the TECH[2:0] pins are all logic zero and auto-negotiation is not
enabled, this bit will be writeable. If auto-negotiation is not enabled
and the TECH[2:0] pins are set to indicate that only 10Base-T is
supported, this bit will be forced to logic zero and will not be writeable.
If auto-negotiation is not enabled and the TECH[2:0] pins are set to
indicate that only 100Base-TX is supported, this bit will be forced to
logic one and will not be writeable. When auto-negotiation is enabled,
this bit will not be writeable and will have no effect on the 78Q2120C.
If the TECH[2:0] pins are brought to zero from another value, this bit
will retain its original value until it is overwritten.
Auto-Negotiation Enable: Setting this bit to ‘1’ shall enable The auto-
negotiation process. This bit can only be set if the ANEGA pin is a
logic one and will default to ‘1’ upon reset in this case. If this bit is
cleared to ‘0’, manual speed and duplex mode selection is
accomplished through bits 0.13 (SPEEDSL) and 0.8 (DUPLEX) of the
Control Register or the TECH[2:0] pins according to the table shown in
the section describing the TECH[2:0] pins.
brought from ‘0’ to ‘1’ and reset is not asserted, this bit will remain at
‘0’ until a ‘1’ is written.
Power-Down: The device may be placed in a low power consumption
state by setting this bit to ‘1’. While in power-down state, the device
will still respond to management transactions. Setting the PWRDN pin
high can also activate the power-down state.
Isolate: When set to ‘1’, the device will present a high-impedance on
its MII output pins. This allows for multiple PHY’s to be attached to
the same MII interface. When the device is isolated, it still responds to
management transactions. The default value of this bit depends on
the ISODEF pin. When ISODEF pin is tied high, the ISO bit defaults
to high. Otherwise, it defaults to low. The Isolate mode can also be
activated through the ISO pin.
Restart Auto-Negotiation: Normally, the Auto-Negotiation process is
started at power up. The process can be restarted by setting this bit
to ‘1’. This bit is self-clearing.
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If the ANEGA pin is
Rev_1.1