78Q2120C Teridian Semiconductor Corp. (TDK Semiconductor), 78Q2120C Datasheet - Page 8

• Manufacturer Part Number: 78Q2120C
• Description: 10/100 Ethernet PHYS
• Manufacturer: Teridian Semiconductor Corp. (TDK Semiconductor)

CONTROL AND STATUS (CONTINUED)
MDI (MEDIA DEPENDENT INTERFACE)
© 2003 TDK Semiconductor Corporation, Proprietary and Confidential
ISO
ISODEF
ANEGA
TECH[2:0]
RPTR
TXOP/N
RXIP/N
NAME
NAME
44-46
61,62
52,51
PIN
PIN
47
50
2
1
TYPE
CID
TYPE
CI
CI
CI
CI
A
A
DESCRIPTION
ISOLATE: When set to logic one, the 78Q2120C will present a high
impedance on its MII output pins.
attached to the same MII interface. When the 78Q2120C is isolated, it still
responds to management transactions. The same high impedance state can
also be achieved through the ISO bit in the MII register (MR0.10).
ISOLATE DEFAULT: This pin determines the power-up/reset default of the
ISO bit (MR0.10). If it is connected to supply, the ISO bit will have a default
value of ‘1’. Otherwise, the bit defaults to ‘0’. When this signal is tied to
supply, it allows multiple chips to be connected to the same MII interface.
AUTO-NEGOTIATION ABILITY: Strapped to logic high to allow auto-
negotiation function. When strapped to logic low, auto-negotiation logic is
disabled and manual technology selection is done through TECH[2:0] pins.
This pin is reflected as the ANEGA bit in MR1.3.
TECHNOLOGY ABILITY/SELECT: TECH[2:0] sets the technology ability of
the chip which is reflected in MR0.13,8, MR1.14:11 and MR4.12:5.
TECH[2:0]
REPEATER MODE: When pulled high, this pin puts the chip into repeater
mode. In this mode, full duplex is prohibited, CRS responds to receive activity
only and, in 10BASE-T mode, the SQE test function is disabled. This mode
can also be entered with MR16.15
DESCRIPTION
TRANSMIT OUTPUT POSITIVE/NEGATIVE: Transmitter differential outputs
for both 10BASE-T and 100BASE-TX operation.
RECEIVE INPUT POSITIVE/NEGATIVE:
both 10BASE-T and 100BASE-TX operation.
111
001
010
011
100
101
110
- 8 -
Technology ability
Both 10BASE-T and 100BASE-TX,
Both half and full duplex
10BASE-T, half duplex
100BASE-TX, half duplex
Both 10BASE-T and 100BASE-TX, half duplex
None
10BASE-T Both half and full duplex
100BASE-TX Both half and full duplex
10/100BASE-TX Transceiver
This allows for multiple chips to be
Receiver differential inputs for
78Q2120C
Rev_1.1