ATA5423 ATMEL Corporation, ATA5423 Datasheet - Page 89

• Manufacturer Part Number: ATA5423
• Manufacturer: ATMEL Corporation

16. Digital Timing Characteristics
All parameters refer to GND and are valid for T
and V
4841A–RKE–02/05
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
12.1
12.2
13.1
13.2
13.3
13.4
No.
12
13
VS2
= 5.0 V (base
Parameters
Basic Clock Cycle of the Digital Circuitry
Basic clock cycle
Extended basic clock
cycle
RX Mode/RX Polling Mode
Sleep time
Start
Start
processing
Time for bit check
–
–
up PLL RX mode from IDLE mode
up signal
–
station application) unless otherwise specified.
Test Conditions
XLIM = 0
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
XLIM = 1
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
Sleep and XSleep are
defined in control
register 4
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
Average time during
polling. No RF signal
applied.
f
Signal data rate
Manchester
(Lim_min and Lim_max
up to ±50% of t
see
Figure 9-4 on page
Bit
valid input signal f
N
N
N
N
Signal
Bit–check
Bit–check
Bit–check
Bit–check
–
check time for a
= 1/(2
= 0
= 3
= 6
= 9
amb
t
= 25°C. V
ee
ee
)
,
Signal
56)
VS1
Pin
= V
S2
= 3.0 V (1
ATA5423/25/28/29 [Preliminary]
T
Startup_Sig_Proc
T
Symbol
T
Startup_PLL
T
T
T
Bit_check
XDCLK
DCLK
Sleep
–
battery application), V
Sleep
X
1024
16/f
3/f
6/f
9/f
T
Sleep
Min.
882
498
306
210
T
T
T
DCLK
16
Signal
Signal
Signal
8
4
2
1
8
4
2
DCLK
DCLK
DCLK
XTO
798.5
1/f
T
Typ.
DCLK
Signal
VS2
= 6.0 V (2
3.5/f
6.5/f
9.5/f
Sleep
798.5
X
1024
16/f
T
T
Max.
Sleep
882
498
306
210
T
T
T
DCLK
DCLK
16
8
4
2
1
8
4
2
DCLK
DCLK
DCLK
Signal
Signal
Signal
XTO
–
battery application)
Unit
ms
ms
µs
µs
µs
Type*
A
A
A
A
A
C
89