ATA5423 ATMEL Corporation, ATA5423 Datasheet - Page 90

• Manufacturer Part Number: ATA5423
• Manufacturer: ATMEL Corporation

16. Digital Timing Characteristics (Continued)
All parameters refer to GND and are valid for T
and V
90
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
13.5
13.6
13.7
14.1
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
15.9
No.
14
15
VS2
= 5.0 V (base
Parameters
Baud
Minimum time period
between edges at pin
SDO_TMDO in RX
transparent mode
Edge
period of the data signal
for full sensitivity in RX
mode
TX Mode
Start
Configuration of the Transceiver with 4–wire Serial Interface
CS set
edge of SCK
SCK cycle time
SDI_TMDI set
to rising edge of SCK
SDI_TMDI hold time
from rising edge of SCK
SDO_TMDO enable
time from rising edge of
CS
SDO_TMDO output
delay from falling edge
of SCK
SDO_TMDO disable
time from falling edge of
CS
CS disable time period
Time period SCK low to
CS high
ATA5423/25/28/29 [Preliminary]
–
–
–
up time
rate range
to
–
up time to rising
–
edge time
–
–
station application) unless otherwise specified.
up time
Test Conditions
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
XLIM = 0
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
XLIM = 1
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
From IDLE mode
C
L
= 10 pF
amb
= 25°C. V
VS1
33, 35
32, 33
32, 33
31, 35
31, 35
31, 33
33, 35
Pin
= V
31
33
35
S2
= 3.0 V (1
BR_Range
T
T
T
T
T
T
T
Symbol
SCK_setup1
Out_disable
Out_enable
T
CS_disable
DATA_min
Out_delay
CS_setup
T
T
T
T
Startup
Cycle
Setup
DATA
Hold
–
battery application), V
T
10
Min.
XDCLK
200
100
250
250
250
1.0
2.0
4.0
8.0
1.5
T
1.5
T
50
25
2
DCLK
DCLK
331.5
Typ.
T
DCLK
VS2
= 6.0 V (2
331.5
Max.
10.0
20.0
62.5
500
250
125
250
250
250
T
2.5
5.0
DCLK
–
battery application)
kBaud
Unit
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
µs
ns
4841A–RKE–02/05
Type*
A
A
B
A
A
A
C
C
C
C
C
A
C