CDK2000 Cirrus Logic, Inc., CDK2000 Datasheet - Page 18

• Manufacturer Part Number: CDK2000
• Description: Fractional-n Clock Multiplier with Internal LCO
• Manufacturer: Cirrus Logic, Inc.

18
5.8
5.8.1
5.8.2
5.9
Clock Output Stability Considerations
Required Power Up Sequencing for Programmed Devices
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Output Switching
The CS2300-OTP is designed such that re-configuration of the clock routing functions do not result in a
partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or
disabling an output, and the automatic disabling of the output(s) during unlock will not cause a runt or par-
tial clock period.
The following exceptions/limitations exist:
• Enabling/disabling AUX_OUT when AuxOutSrc[1:0] = 11 (unlock indicator).
• Switching AuxOutSrc[1:0] to or from 01 (CLK_IN) and to or from 11 (unlock indicator)
When any of these exceptions occur, a partial clock period on the output may result.
PLL Unlock Conditions
Certain changes to the clock inputs and mode pins can cause the PLL to lose lock which will affect the
presence of a clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go un-
locked:
• Any change in the state of the M1 and M0 pins will cause the PLL to temporarily lose lock as the new
• Changes made to the state of the M2 when the M2Config[2:0] global parameter is set to 011, 100, 101,
• Discontinuities on the Frequency Reference Clock, CLK_IN.
• Gradual changes in CLK_IN frequency greater than ±30% from the starting frequency.
• Step changes in CLK_IN frequency.
ification in the
the device. This must be done after the power supply is stable and before normal operation is expected.
Note: This operation is not required for factory programmed devices.
figured by the M0-M2 pins.
Apply power. All input pins should be held in a static logic hi or lo state until the
Apply input clock.
For CDK programmed devices, toggle the state of the M0, M1, or both pins at least 3 times to initialize
After the specified PLL lock time on
(Transitions between AuxOutSrc[1:0] = [00,10] will not produce a glitch).
setting takes affect.
or 110 can cause the PLL to temporarily lose lock as the new setting takes affect.
“Recommended Operating Conditions” table on page 6
page 7
has passed, the device will output the desired clock as con-
are met.
‘DC Power
CS2300-OTP
Supply’ spec-
DS844F1