PAC80 Lattice Semiconductor Corp., PAC80 Datasheet - Page 14

• Manufacturer Part Number: PAC80
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

In-System Programming
The ispPAC80 is an in-system programmable device.
This is accomplished by integrating all high voltage
programming circuitry on-chip. Programming is performed
through a 5-wire, IEEE 1149.1 compliant serial port
interface at normal logic levels. Once a device is pro-
grammed, all configuration information is stored on-chip,
in non-volatile E
the IEEE 1149.1 serial interface are described in the
interface section of this data sheet.
User Electronic Signature
A user electronic signature (UES) feature is included in
the E
can be configured by the user to store unique data such
as ID codes, revision numbers or inventory control data.
Electronic Security
An electronic security “fuse” (ESF) bit is provided in every
ispPAC80 device to prevent unauthorized readout of the
E
prevents further access to the functional user bits in the
device. This cell can only be erased by reprogramming
Figure 4. Configuring the ispPAC80 “In-System” from a PC Parallel Port
In-System Programmability
2
CMOS user bit patterns. Once programmed, this cell
2
memory of the ispPAC80. It contains 21 bits that
2
CMOS memory cells. The specifics of
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the device, so the original configuration can not be
examined once programmed. Usage of this feature is
optional.
Production Programming Support
Once a final configuration is determined, an ASCII format
JEDEC file is created using the PAC-Designer software.
Devices can then be ordered through the usual supply
channels with the user’s specific configuration already
preloaded into the devices. By virtue of its standard
interface, compatibility is maintained with existing pro-
duction programming equipment, giving customers a
wide degree of freedom and flexibility in production
planning.
Evaluation Fixture
Included in the basic ispPAC80 Design Kit is an engineer-
ing prototype board that can be connected to the parallel
port of a PC. It demonstrates proper layout techniques for
the ispPAC80 and can be used in real time to check
circuit operation as part of the design process. Input and
output connections as well as a “breadboard” circuit area
are provided to speed debugging of the circuit.
Specifications ispPAC80