WM8141 Wolfson Microelectronics Ltd., WM8141 Datasheet - Page 12

• Manufacturer Part Number: WM8141
• Description: WM8141 : 12-BIT 6MSPS Cis/ccd Analogue Front End/digitiser
• Manufacturer: Wolfson Microelectronics Ltd.

WM8141
CDS/NON-CDS PROCESSING
WOLFSON MICROELECTRONICS LTD
Figure 6 Reset Level Clamping and CDS Circuitry
If auto-cycling is not required, RLC can be selected by pin RLC/ACYC. Figure 6 illustrates control of
RLC for a typical CCD waveform, with CL applied during the reset period.
The input signal applied to the RLC pin is sampled on the positive edge of MCLK that occurs during
each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal
CL pulse on the next reset level. The position of CL can be adjusted by using control bits
CDSREF[1:0] (Figure 7).
If auto-cycling is required, pin RLC/ACYC is no longer available for this function and control bit
RLCINT determines whether clamping is applied.
Figure 7 Relationship of RLC Pin, MCLK and VSMP to Internal Clamp Pulse, CL
The VRLC/VBIAS pin can be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits
RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit
RLCDACRNG. Alternatively, the VRLC/VBIAS pin can be driven externally by writing to control bit
VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin.
For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel
common mode noise. For CDS operation, the video level is processed with respect to the video reset
level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must
be set to 1 (default), this controls switch 2 (Figure 6) and causes the signal reference to come from
the video reset level. The time at which the reset level is sampled, by clock R
programming control bits CDSREF[1:0], as shown in Figure 8.
(CDSREF = 01)
INPUT VIDEO
RLC/ACYC
EXTERNAL VRLC
MCLK
VSMP
CL
C
RGB
1
IN
VRLC/
VBIAS
RINP
Programmable Delay
X
1
RLC
CL
2
RLC/ACYC
X
VRLCEXT
TIMING CONTROL
RLC DAC
4-BIT
RLC on this Pixel
S/H
R
S
CDS
CDS
MCLK
RGB
0
S/H
V
S
VSMP
X
INPUT SAMPLING
BLOCK FOR RED
CHANNEL
+
-
+
s
/CL, is adjustable by
X
FROM CONTROL
INTERFACE
TO OFFSET DAC
FROM CONTROL
INTERFACE
PD Rev 3.0 October 2000
No RLC on this Pixel
Production Data
RGB
0
12