WM8141 Wolfson Microelectronics Ltd., WM8141 Datasheet - Page 14

• Manufacturer Part Number: WM8141
• Description: WM8141 : 12-BIT 6MSPS Cis/ccd Analogue Front End/digitiser
• Manufacturer: Wolfson Microelectronics Ltd.

WM8141
CALCULATING OUTPUT FOR ANY GIVEN INPUT
WOLFSON MICROELECTRONICS LTD
The INPUT SAMPLING BLOCK produces an effective input voltage V
difference between the input video level V
difference between the input video level V
optionally set via the RLC DAC.
The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the
black level of the input signal towards 0V, producing V
The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,
outputting voltage V
The ADC BLOCK then converts the analogue signal, V
The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D
The following equations describe the processing of the video and reset level signals through
the WM8141.
INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING
If CDS = 1, (i.e. CDS operation) the previously sampled reset level, V
input video.
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted
instead.
If RLCEXT = 1, V
If RLCEXT = 0, V
V
OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST
The resultant signal V
PGA NODE: GAIN ADJUST
The signal is then multiplied by the PGA gain,
ADC BLOCK: ANALOGUE-DIGITAL CONVERSION
The analogue signal is then converted to a 12-bit unsigned number, with input range configured by
PGAFS[1:0].
where the ADC full-scale range, V
OUTPUT INVERT BLOCK: POLARITY ADJUST
The polarity of the digital output may be inverted by control bit INVOP.
RLCSTEP
is the step size of the RLC DAC and V
V
V
V
V
V
D
D
D
D
D
1
1
VRLC
2
3
1
1
1
2
2
[11:0] = INT{ (V
[11:0] = INT{ (V
[11:0] = INT{ (V
[11:0] = D
[11:0] = 4095 – D
VRLC
VRLC
=
=
=
=
=
3
.
1
is an externally applied voltage on pin VRLC/VBIAS.
is the output from the internal RLC DAC.
1
[11:0]
is added to the Offset DAC output.
V
V
(V
V
V
IN
IN
1
2
3
3
3
RLCSTEP
+ {260mV
/V
/V
/V
- V
- V
1
208/(283- PGA[7:0]) .............................................. Eqn. 5
[11:0]
FS
FS
FS
RESET
VRLC
)
)
)
FS
4095} + 2047
4095}
4095} + 4095
= 3V at AVDD=5V and V
RLCV[3:0]) + V
.................................................................... Eqn. 2
................................................................... Eqn. 1
(DAC[7:0]-127.5) } / 27.5 ....................... Eqn. 4
IN
and the input reset level V
IN
RLCBOT
and the voltage on the VRLC/VBIAS pin, V
RLCBOT
(INVOP = 0) ...................... Eqn. 9
(INVOP = 1) ...................... Eqn. 10
PGAFS[1:0] = 00 or 01 ...... Eqn. 6
PGAFS[1:0] = 11 ............... Eqn. 7
PGAFS[1:0] = 10 ............... Eqn. 8
2
is the minimum output of the RLC DAC.
.
3
, to a 12-bit unsigned digital output, D
................................. Eqn. 3
FS
= 1.5V at AVDD=3.3V
RESET
RESET
1
. For non-CDS this is the
. For CDS, this is the
, is subtracted from the
PD Rev 3.0 October 2000
Production Data
1
.
VRLC
2.
14
,