WM8141 Wolfson Microelectronics Ltd., WM8141 Datasheet - Page 24

• Manufacturer Part Number: WM8141
• Description: WM8141 : 12-BIT 6MSPS Cis/ccd Analogue Front End/digitiser
• Manufacturer: Wolfson Microelectronics Ltd.

WM8141
WOLFSON MICROELECTRONICS LTD
Setup
Register 2
Setup
Register 3
Software
Reset
Auto-cycle
Reset
Setup
Register 4
REGISTER
BIT
1:0
7:6
3:0
5:4
7:6
5:4
7:6
NO
2
3
5
0
1
2
3
RLCDACRNG
CDSREF[1:0]
LINEBYLINE
MUXOP[1:0]
ACYCNRLC
CHAN[1:0]
VRLCEXT
RLCV[3:0]
INTM[1:0]
NAME(S)
DEL[1:0]
RLCINT
FM[1:0]
INVOP
FME
BIT
DEFAULT
1111
00
01
00
00
00
0
0
0
1
0
0
0
0
DESCRIPTION
Determines the output data format.
00 = 12-bit output
01 = 8-bit multiplexed (8+4 bits)
Digitally inverts the polarity of output data.
0 = negative going video gives negative going output.
1 = negative-going video gives positive going output data.
When set powers down the RLCDAC, changing its output to Hi-Z, allowing
VRLC to be externally driven.
Sets the output range of the RLCDAC.
0 = RLCDAC ranges from 0 to AVDD (approximately).
1 = RLCDAC ranges from 0 to VRT (approximately).
Sets the output latency in ADC clock periods.
1 ADC clock period = 2 MCLK periods except in mode 3 where 1 ADC clock
period = 3 MCLK periods.
00 = Minimum latency
01 = Delay by one ADC
clock period
Controls RLCDAC driving VRLC pin to define single ended signal reference
voltage or Reset Level Clamp voltage. See Electrical Characteristics section
for ranges.
CDS mode reset timing adjust.
00 = Advance 1 MCLK period
01 = Normal
Monochrome mode channel select.
00 = Red channel select
01 = Green channel select
Any write to Software Reset causes all cells to be reset.
Any write to Auto-cycle Reset causes the auto-cycle counter to reset
to RINP.
Selects line by line operation 0 = normal operation,
1 = line by line operation.
When line by line operation is selected MONO is forced to 1 and CHAN[1:0]
to 00 internally, ensuring that the correct internal timing signals are
produced. Green and Blue PGAs are also disabled to save power.
When LINEBYLINE = 0 this bit has no effect.
When LINEBYLINE = 1 this bit determines the function of the RLC/ACYC
input pin and the input multiplexer and offset/gain register controls.
0 = RLC/ACYC pin enabled for Reset Level Clamp. Internal selection of
input and gain/offset multiplexers.
1 = Auto-cycling enabled by pulsing the RLC/ACYC input pin.
See Table 4, Colour Selection Description in Line-by-Line Mode for colour
selection mode details.
When auto-cycling is enabled, the RLC/ACYC pin cannot be used for reset
level clamping. The RLCINT bit may be used instead.
When LINEBYLINE = 0 this bit has no effect.
When LINEBYLINE = 1 this bit controls the input force mux mode:
0 = No force mux, 1 = Force mux mode. Forces the input mux to be selected
by FM[1:0] separately from gain and offset multiplexers.
See Table 4 for details.
When LINEBYLINE = 1 and ACYCNRLC = 1 this bit is used to determine
whether Reset Level Clamping is used.
0 = RLC disabled, 1 = RLC enabled.
Colour selection bits used in internal modes. See Table 4 for details.
00 = Red, 01 = Green, 10 = Blue and 11 = Reserved.
Colour selection bits used in input force mux modes.
See Table 4 for details.
00 = Red, 01 = Green, 10 = Blue and 11 = Reserved.
10 = 6-bit multiplexed mode (6+6 bits)
11 = 4-bit multiplexed mode (4+4+4 bits)
10 = Delay by two ADC clock periods
11 = Delay by three ADC clock periods
10 = Retard 1 MCLK period
11 = Retard 2 MCLK periods
10 = Blue channel select
11 = Reserved
PD Rev 3.0 October 2000
Production Data
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