WM8144-10 Wolfson Microelectronics Ltd., WM8144-10 Datasheet - Page 13

• Manufacturer Part Number: WM8144-10
• Description: Integrated 10-bit Data Acquisition System For Imaging Applications
• Manufacturer: Wolfson Microelectronics Ltd.

Theory of Operation (contd.)
Digital Signal Processing
By default, the output from the ADC passes through the
digital compensation block without being altered and is
output directly on the OP[9:0] pins. If required, the pixel
data from the ADC can be processed further by the dig-
ital compensation block (Figure 8). This section describes
the sub-blocks of the digital compensation block.
CDATA Demultiplexor
The input to this block is coefficient data presented to the
CDATA[7:0] pins at twice the pixel rate. i.e. two eight-bit
words are input for each pixel of video data.
Data Partitioning
The sixteen bits of data per pixel from the CDATA
Demultiplexor is partitioned into pixel offset, pixel gain
and pixel valid bits (Table 3) . Table 4 details the resulting
range and resolution options.
Pixel Offset Adder
This uses the offset coefficients that are either supplied
externally via the CDATA interface or from the internal
default registers. The object of this block is to correct for
the small offsets which can occur from the CCD on a
pixel-by-pixel basis. The output from the Pixel Offset
Adder is limited to be between 0 and 1023(dec).
Pixel Gain Adjust
This block corrects for the pixel-by-pixel shading curve
non-uniformity and photo response non-uniformity within
the CCD sensor. This block has a gain range of 0 to 2.
The output word from the Pixel Gain Adjust is limited to
between 0 and 1023(dec).
CDATA
ADCOP
Figure 8
DEFAULT
10
Figure 12
PIXEL OFFSET
AND MUX
DEMUX
ADDER
6
MUX
4,5 or 6
11
PARTITIONING
LIMIT
DATA
Wolfson Microelectronics
DEFAULT
12,11 or 10
10
PIXEL GAIN
ADJUST
MUX
MUX
MUX
12
DEFAULT
Effect of digital compensation on ADC output
The combined effect of the digital compensation sec-
tions on the ADC output is summarised by the formula:
where:
All values are decimal
OP[9:0] is the 10 bit result output from the WM8144-10
ADCOP is a 10 bit unsigned number from the ADC
POC is a 2's compliment number divided byNUMBER OF
POC BITS ALLOCATED/2
PSCF is an unsigned number divided by NUMBER OF
PSC BITS ALLOCATED/2
For this example assume PSC is allocated 12 bits and
POC
3:DVMODE,PWP0,PWP1 = 0). Table 1 shows some ex-
amples of the effect of the digital backend on the ADC
output.
Table 2: Examples of digital backend calculation
22
Default
Range
Ex 1
Ex 2
Ex 3
Ex 4
Ex 5
Ex 6
Ex 7
Ex 8
Ex 9
GENERATION
ADC
DATA VALID
OP[9:0] = (ADCOP + POC) * PSCF
is
LIMIT
ADCOP
0:1023
1022
1022
512
512
512
512
512
512
511
allocated
10
POC
-8:7
-7
OUT OF RANGE
0
0
6
6
6
0
0
0
0
GENERATION
LATCH
DATA
4
2048 (x1)
0:4095
bits
2048
2048
2048
2048
2560
4095
4095
PSC
512
512
WM8144-10
10
(refer
OP[9:0]
0:1023
1023
1023
1021
DV OUTPUT
OP[9:0] INPUT TO
8/10 MUX BLOCK
ORNG INPUT TO
8/10 MUX BLOCK
512
505
518
257
640
128
to
ORNG
0:1
0
0
0
1
1
0
0
1
0
table
13