WM8144-10 Wolfson Microelectronics Ltd., WM8144-10 Datasheet - Page 21

• Manufacturer Part Number: WM8144-10
• Description: Integrated 10-bit Data Acquisition System For Imaging Applications
• Manufacturer: Wolfson Microelectronics Ltd.

Configuration of the WM8144-10
The WM8144-10 can be configured through a serial
interface or a parallel interface. Selection of the
interface type is by the PNS pin which must be tied
high (parallel) or low (serial).
Serial Interface
The serial interface consists of three pins (refer to
figure 16 ). A six-bit address is clocked in MSB first
followed by an eight-bit data word, also MSB first.
Each bit is latched on the rising edge of SCK, which
can operate at upto 12MHz. Once the data has been
shifted into the device, a pulse is applied to SEN to
transfer the data to the appropriate internal register.
Parallel Interface
The parallel interface uses bits [9:2] of the OP bus as
well as the STB, DNA and RNW pins (refer to figure
17). Pin RNW must be low during a write operation.
The DNA pin defines whether the data byte is address
(low) or data (high). The data bus OP[9:2] is latched in
during the low period of STB. This interface is
compatible with the Extended Parallel Port interface.
Internal Register Definition
Table 5 summarises the internal register content. The
first 4 addresses in the table are used to program setup
registers and to provide a software reset feature ( 00H
is reserved ). The remaining 7 entries in the table define
Table 6: Register Map Contents
Address
<a5:a0>
000000 Reserved
000001 Setup Register 1
000010 Setup Register 2
000011 Setup Register 3
000100 Software Reset
000101 Setup Register 4
1000xx DAC values
1001xx DAC signs
1010xx PGA Gains
1011xx Pixel Offsets
1100xx Pixel Gain MSB
1101xx Pixel Gain LSB
1110xx Data Valid
xx
Address LSB decode
Red Register
Green Register
Blue Register
Red, Green and Blue
Description
Def'lt
(Hex)
1B
00
11
00
00
00
00
00
00
80
00
01
DVMODE
GAIN[11]
CHAN[1]
DAC[7]
b7
a1
0
0
1
1
Wolfson Microelectronics
VSMP6M
GAIN[10]
CHAN[0]
DAC[6]
b6
a0
0
1
0
1
CDSREF[1] CDSREF[0]
CDATOUT
GAIN[9]
DEFDV
DAC[5]
OFF[5]
b5
the address location of internal data registers. In each case,
a further three sub-addresses are defined for the red, green
and blue register. Selection between the red, green and
blue registers is performed by address bits a1 and a0, as
defined in the table. Setting both a1 and a0 equal to 1 forces
all three registers to be updated to the same data value.
Blank entries can be taken as 'don't care' values.
Figure 16: Serial Interface Timing
Figure 17: Parallel Interface Timing
BYPASS
GAIN[8]
DEFPO
DAC[4]
PGA[4]
OFF[4]
b4
Bit
LATCHOP
GAIN[7]
GAIN[3]
DEFPG
PWP[1]
DAC[3]
PGA[3]
OFF[3]
b3
PWP[0]
GAIN[6]
GAIN[2]
DAC[2]
PGA[2]
MONO
INVOP
OFF[2]
b2
WM8144-10
DACRNG
GAIN[5]
GAIN[1]
DAC[1]
PGA[1]
RLC[1]
OFF[1]
CDS
b1
MUXOP
ENADC
GAIN[4]
GAIN[0]
DAC[0]
DSIGN
PGA[0]
RLC[0]
OFF[0]
DV
b0
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