WM8581SEFT Wolfson Microelectronics Ltd., WM8581SEFT Datasheet - Page 25

• Manufacturer Part Number: WM8581SEFT
• Description: Multichannel Codec with S/pdif Transceiver
• Manufacturer: Wolfson Microelectronics Ltd.

Product Preview
w
Figure 15 Right Justified Mode Timing Diagram
I
In I
LRCLK transition. The MSB of the output data changes on the first falling edge of BCLK following an
LRCLK transition, and may be sampled on the next rising edge of BCLK. LRCLKs are low during the
left samples and high during the right samples.
Figure 16 I
DSP MODE A
In DSP Mode A, the MSB of Channel 1 left data is sampled on the second rising edge of BCLK following a
LRCLK rising edge. Channel 1 right data then follows. For the PAIF Receiver, Channels 2 , 3 and 4 follow as
shown in Figure 17.
Figure 17 DSP Mode A Timing Diagram – PAIF Receiver Input Data
2
S MODE
2
S mode, the MSB of DIN1/2/3/4 is sampled on the second rising edge of BCLK following a
2
S Mode Timing Diagram
PP Rev 1.0 March 2006
WM8581
25