WM8581SEFT Wolfson Microelectronics Ltd., WM8581SEFT Datasheet - Page 53

• Manufacturer Part Number: WM8581SEFT
• Description: Multichannel Codec with S/pdif Transceiver
• Manufacturer: Wolfson Microelectronics Ltd.

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PHASE-LOCKED LOOPS AND S/PDIF CLOCKING (HARDWARE MODE)
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The recommended configuration sequences are as follows:
TO INITIALLY CONFIGURE THE SYSTEM FOR S/PDIF RECEIVER STARTUP:
TO CONFIGURE THE SYSTEM WHEN CLOCKING MODE (SAMPLE RATE) CHANGES TO OR FROM
MODE 1 (192KHZ):
Any sample rate change between clocking modes (for example, from 44.1kHz (mode 3) to 192kHz (mode 1))
will be flagged to the application processor via the INT interrupt flag. The application processor must then
read the Interrupt Status Register. If the UPD_REC_FREQ flag is set, indicating that the clocking mode has
changed, proceed as follows:
This procedure is only strictly necessary when switching to or from 192kHz (mode 1) because the
PRESCALE_A,
32/44.1/48/88.2/96kHz (modes 2/3/4) sample rate operation. It is, however, good interrupt service
routine practice to write the appropriate PRESCALE_A, PRESCALE_B, PLLB_N and PLLB_K values
when every clocking mode change is detected.
In hardware mode, the user has no access to the internal clocking control registers and hence a default
configuration is loaded at reset to provide maximum functionality.
The S/PDIF receiver is enabled and hence the PLLs operate in S/PDIF receiver mode and all PLL and
S/PDIF receiver control is fully automatic. All supported S/PDIF receiver sample rates can be used.
FREQMODE_x and POSTSCALE_x control is fully automatic to ensure that the MCLK output is maintained
at 256fs relative to the S/PDIF received sample rate.
In hardware mode, the OSCCLK must be 12MHz and hence the external crystal (or applied XIN clock) must
be 12MHz. No other OSCCLK frequencies are supported in hardware mode.
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Write appropriate calculated values (relative to oscillator frequency) to PRESCALE_A,
PRESCALE_B, PLLB_N and PLLB_K for 32/44.1/48/88.2/96kHz (modes 2/3/4) S/PDIF
receiver sample rate operation.
Enable PLLA and PLLB by clearing the PLLAPD and PLLBPD bits.
Enable S/PDIF receiver by clearing the SPDIFRXPD and SPDIFPD bits.
Read S/PDIF Status Register REC_FREQ[1:0] bits to identify recovered S/PDIF sample
frequency and clocking mode.
If indicated sample rate is 192kHz, write appropriate calculated values (relative to oscillator
frequency) to PRESCALE_A, PRESCALE_B, PLLB_N and PLLB_K (as appropriate) for
192kHz (mode 1) S/PDIF receiver sample rate operation.
Read S/PDIF Status Register REC_FREQ[1:0] bits to identify recovered S/PDIF sample rate
frequency and clocking mode.
Write appropriate calculated values (relative to oscillator frequency) to PRESCALE_A,
PRESCALE_B, PLLB_N and PLLB_K based on indicated recovered S/PDIF sample
frequency and clocking mode.
PRESCALE_B,
PLLB_N
and
PLLB_K
values
PP Rev 1.0 March 2006
are
the
WM8581
same
for
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