WM8581SEFT Wolfson Microelectronics Ltd., WM8581SEFT Datasheet - Page 50

• Manufacturer Part Number: WM8581SEFT
• Description: Multichannel Codec with S/pdif Transceiver
• Manufacturer: Wolfson Microelectronics Ltd.

WM8581
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Table 43 PLL S/PDIF Receiver Mode Clock Divider Configuration
PLL CONFIGURATION EXAMPLE
Consider the situation where the oscillator clock (OSCCLK) input frequency is fixed at 12MHz and the
required PLLBCLK frequency is 12.288MHz.
The value of PLLB_N is the integer (whole number) value of R, ignoring all digits to the right of the decimal
point. In this case, R is 8.192, hence PLLB_N is 8.
The PLLB_K value is simply the integer value of (2
A number of example configurations are shown in Table 44. Many other configurations are possible; Table 44
shows only a small number of valid possibilities. As both PLLs are identical, the same configuration
procedure applies for both.
1.
The PLL is designed to operate with best performance when the f
necessary PLLBCLK frequency is 12.288MHz. Choose POSTSCALE_B and FREQMODE_B values to set
the f
FREQMODE_B[1:0] = 10) will configure the f
98.304MHz; this value is within the 90 to 100MHz range and is hence acceptable.
2.
Using the relationship: R = (f
3.
4.
2
POSTSCALE_A
Calculate the f
Calculate R Value
Calculate PLLB_N Value
Calculate PLL_K Value
frequency in the range of 90 to 100MHz. In this case, the default values (POSTSCALE_B = 0 and
POSTSCALE_B = 0
FREQMODE_B [1:0] = 10b
f
2
= 98.304MHz
0
1
R = (f
R = (98.304 ÷ 12)
R = 8.192
PLLB_K = integer part of (2
PLLB_K = integer part of 805306.368
PLLB_K = 805306 (decimal) / C49BA (hex)
2
, FREQMODE_B and POSTSCALE_B Values
2
÷ f
1
)
2
÷ f
1
), the value of R can be calculated.
PLLACLK FREQUENCY
22
2
x (8.192 – 8))
to PLLBCLK divider as 8 and hence will set the f
256fs
128fs
22
(R-PLLB_N)).
2
clock is between 90 and 100MHz. The
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2
frequency at
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