MAX5874 Maxim Integrated Products, MAX5874 Datasheet - Page 12

• Manufacturer Part Number: MAX5874
• Description: Dual DAC with LVDS Inputs
• Manufacturer: Maxim Integrated Products

14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
Figure 4. Timing Relationships Between Clock and Input Data for (a) Dual-Port (Parallel) Mode and (b) Single-Port (Interleaved) Mode
The MAX5874 features a flexible differential clock input
(CLKP, CLKN) with a separate supply (AV
achieve optimum jitter performance. Use an ultra-low
jitter clock to achieve the required noise density. Clock
jitter must be less than 0.5ps
fied noise density. For that reason, the CLKP/CLKN
input source must be designed carefully. The differen-
tial clock (CLKN and CLKP) input can be driven from a
single-ended or a differential clock source. Differential
12
DATA
Q OUT
SELIQ
I OUT
______________________________________________________________________________________
DATA13–DATA0, XOR
CLK
IN
Q - 6
DAC OUTPUT
I - 6
CLK
Applications Information
t
N - 6
S
N - 1
I0
t
PD
t
RMS
H
Q - 5
I - 5
for meeting the speci-
CLK Interface
Q0
t
S
N - 5
t
PD
(b) SINGLE-PORT (INTERLEAVED) TIMING DIAGRAM
N
(a) DUAL-PORT (PARALLEL) TIMING DIAGRAM
CLK
I1
t
) to
H
clock drive is required to achieve the best dynamic
performance from the DAC. For single-ended opera-
tion, drive CLKP with a low-noise source and bypass
CLKN to GND with a 0.1µF capacitor.
Figure 5 shows a convenient and quick way to apply a
differential signal created from a single-ended source
(e.g., HP 8662A signal generator) and a wideband
transformer. Alternatively, these inputs can be driven
from a CMOS-compatible clock source; however, it is
recommended to use sinewave or AC-coupled differen-
tial ECL/PECL drive for best dynamic performance.
N - 4
Q1
Q - 4
I - 4
N + 1
I2
N - 3
Q2
Q - 3
I - 3
N + 2
I3
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N - 2
Q - 2
I - 2
Q3