DM336P Davicom Semiconductor Incorporated, DM336P Datasheet - Page 10

• Manufacturer Part Number: DM336P
• Manufacturer: Davicom Semiconductor Incorporated

c. Interrupt Identification Register (IIR): Address 2
Reset State 01h, Read only
In order to provide minimum software overhead
during data transfers, the virtual UART prioritizes
interrupts into four levels as followed: Receiver Line
Status (priority 1), Receiver Data Available (priority 2),
Character Timeout Indication (priority 2, FIFO mode
only), Transmitter Holding Register Empty (priority 3 ),
and Modem Status (priority 4).
The IIR register gives prioritized information as to the
status of interrupt conditions. When accessed, the IIR
indicates the highest priority interrupt that is pending,
as indicated by bits INTD(2-0).
10
Enable
D3 D2 D1 D0 Priority Level
FIFO
bit7 bit6 bit5 bit4 bit3
0
0
0
1
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
INTD2
D3:
Highest
Second
Second
Fourth
Third
-
INTD1
bit2
D2:
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
INTD0
bit1
D1:
Receiver Line
Status
Receiver Data
Available
Character
Timeout
Indication
Transmitter
Holding Register
Empty
Modem Status
Interrupt Type
Pending
bit0
-
D0:
int
Overrun Error, Parity
Error, Framing Error or
Break Interrupt
Receiver Data Available
or Trigger Level Reached
No characters have been
read from or written to the
Rx FIFO during
programming time
interval, and the Rx FIFO
is not empty
Transmitter Holding
Register Empty
Clear to Send, Data Set
Ready, Ring Indicator or
Data Carrier Detected
Bit 0: This bit can be used in either a prioritized
Bit 1-2: These two bits of the IIR are used to identify
Bit 3: In character mode, this bit is 0. In FIFO mode,
Bit 4-6: Not used
Bit 7: This bit is set when FCR0 = 1.
interrupt or polled environment to indicate
whether an interrupt is pending. When this bit is
a logic 0, an interrupt is pending, and the IIR
contents may be used as a pointer to the
appropriate interrupt service routine. When bit 0
is a logic 1, no interrupt is pending, and polling
(if used) continues.
this bit is set, along with bit 2, when a timeout
interrupt is pending.
Condition
the highest priority interrupt pending, as
indicated in the table below.
-
Reads the Line Status
Register
Reads the Receiver
Buffer Register or the
FIFO Drops Below The
Threshold Value
Reads The Receiver
Buffer Register
Reads the IIR Register or
(if source of interrupt)
Writes To The Transmitter
Holding Register
Reads the Modem Status
Register
Version: DM336P-DS-F02
DM336P
Reset
-
August 15, 2000
Final