DM336P Davicom Semiconductor Incorporated, DM336P Datasheet - Page 9

• Manufacturer Part Number: DM336P
• Manufacturer: Davicom Semiconductor Incorporated

d. Modem Output Port Register: Address D000H
Write only
These 4 bits work as output ports in response to the
88th, 89th, 90th and 47th pins of this chip (see pin
description).
e. PnP Isolation & Resource Data Port: Address
Write only
The PnP isolation and resource data can be byte-
sequentially written to the corresponding memory
(built-in SRAM) through this register.
f. Auto-configuration Register: Address F400H
The default I/O base and IRQ data stored in 94C46
should be loaded to this register by micro-controller,
and then enable the default configuration. Micro-
controller can also get the current I/O base and IRQ
information by a read from this register.
The configuration determined by this register should
be disabled when the register detects the Initiation
Key described in the next section.
Bit 6: When this bit is set to inform micro-controller
Bit 7: When bit 7 is set, it enables hardware
Final
Version: DM336P-DS-F02
August 15, 2000
bit2 bit1 bit0 IRQ bit5 bit4 bit3
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0
0
0
0
1
1
1
1
F800H
that the current I/O base and IRQ data should
be stored to 93C46 as the default setting at the
next power-on reset through programming the
Auto-configuration Register, this bit should be
cleared by micro-controller.
configuration set according to bit 0-bit 5
(Jumper mode) and load the proper value of
PnP Registers including I/O and Interrupt
Configuration Registers. This bit will be reset,
when it receives PnP Initial Key sequence.
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
10
11
12
15
3
4
5
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
PO0 SEL2 SEL1 /POR
0
1
0 03E8-03EF(COM3)
1 02E8-02EF(COM4)
0
1
0 03E0-03E7(COM7)
1 02E0-02E7(COM8)
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
03F8-03FF(COM1)
02F8-02FF(COM2)
03F0-03F7(COM5)
02F0-02F7(COM6)
I/O
* When reset condition occurred, the I/O and Interrupt
4. UART(16550A) Emulation Registers
a. Receiver Buffer (Read), Transmitter Holding
Address: 0 (DLAB=0) Reset State 00h
When this register address is read, it contains the
parallel received data. Data to be transmitted is
written to this register.
b. Interrupt Enable Register (IER): Address 1
Reset State 00h, Write Only
This 8-bit register enables the four types of interrupts
as described below. Each interrupt source can
activate the INT output signal if enabled by this
register. Resetting bits 0 through 3 will disable all
UART interrupts.
Bit 0: This bit enables the Received Data Available
Bit 1: This bit enables the Transmitter Holding
Bit 2: This bit enables the Receiver Line Status
Bit 3: This bit enables the MODEM Status Interrupt
Bit 4-7: Not used
bit7 bit6 bit
dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0
configuration registers must be reset to default
value according to bit 0 - bit 5.
Register (Write)
Interrupt (and timeout interrupts in the FIFO
mode) when set to logic 1.
Register Empty Interrupt when set to logic 1.
Interrupt when set to logic 1.
when set to logic 1.
0
5
0
bit4
0
Mode
mStatu
Enable
bit3
Intr
s
Enable
Status
Line
bit2
Intr
DM336P
Holdin
Regist
Enable
bit1
Intr
TX
er
g
Enable
Data
bit0
Intr
RX
9