LPC2119 Philips Semiconductors (Acquired by NXP), LPC2119 Datasheet - Page 11

• Manufacturer Part Number: LPC2119
• Description: Single-chip 16/32-bit Microcontrollers; 128/256 KB Isp/iap Flash With 10-bit ADC And CANthe LPC2119/LPC2129 Are Based on a 16/32 Bit ARM7TDMI-STM Cpu With Real-time Emulation And Embedded Trace Support, Together With 128/256 Kilobytes (kB) of Embedde
• Manufacturer: Philips Semiconductors (Acquired by NXP)

Philips Semiconductors
9397 750 12806
Preliminary data
6.5.1 Interrupt sources
Fast Interrupt reQuest (FIQ) has the highest priority. If more than one request is
assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the
ARM processor. The fastest possible FIQ latency is achieved when only one request
is classified as FIQ, because then the FIQ service routine can simply start dealing
with that device. But if more than one request is assigned to the FIQ class, the FIQ
service routine can read a word from the VIC that identifies which FIQ source(s) is
(are) requesting an interrupt.
Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be
assigned to this category. Any of the interrupt requests can be assigned to any of the
16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the
lowest.
Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to
produce the IRQ signal to the ARM processor. The IRQ service routine can start by
reading a register from the VIC and jumping there. If any of the vectored IRQs are
requesting, the VIC provides the address of the highest-priority requesting IRQs
service routine, otherwise it provides the address of a default routine that is shared by
all the non-vectored IRQs. The default routine can read another VIC register to see
what IRQs are active.
Table 4
has one interrupt line connected to the Vectored Interrupt Controller, but may have
several internal interrupt flags. Individual interrupt flags may also represent more than
one interrupt source.
Table 4:
Block
WDT
-
ARM Core
ARM Core
Timer0
Timer1
UART0
UART1
PWM0
lists the interrupt sources for each peripheral function. Each peripheral device
Interrupt sources
Flag(s)
Watchdog Interrupt (WDINT)
Reserved for software interrupts only
Embedded ICE, DbgCommRx
Embedded ICE, DbgCommTx
Match 0 - 3 (MR0, MR1, MR2, MR3)
Capture 0 - 3 (CR0, CR1, CR2, CR3)
Match 0 - 3 (MR0, MR1, MR2, MR3)
Capture 0 - 3 (CR0, CR1, CR2, CR3)
Rx Line Status (RLS)
Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Rx Line Status (RLS)
Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Status Interrupt (MSI)
Match 0 - 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)
Rev. 02 — 02 February 2004
Single-chip 16/32-bit microcontrollers
LPC2119/LPC2129
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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