LPC2119 Philips Semiconductors (Acquired by NXP), LPC2119 Datasheet - Page 21

• Manufacturer Part Number: LPC2119
• Description: Single-chip 16/32-bit Microcontrollers; 128/256 KB Isp/iap Flash With 10-bit ADC And CANthe LPC2119/LPC2129 Are Based on a 16/32 Bit ARM7TDMI-STM Cpu With Real-time Emulation And Embedded Trace Support, Together With 128/256 Kilobytes (kB) of Embedde
• Manufacturer: Philips Semiconductors (Acquired by NXP)

Philips Semiconductors
9397 750 12806
Preliminary data
6.20.1 Crystal oscillator
6.20.2 PLL
6.20.3 Reset and wake-up timer
6.20 System control
The oscillator supports crystals in the range of 1 MHz to 30 MHz. The oscillator
output frequency is called f
as cclk for purposes of rate equations, etc. f
the PLL is running and connected. Refer to
information.
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The
input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current
Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in
practice, the multiplier value cannot be higher than 6 on this family of microcontrollers
due to the upper frequency limit of the CPU). The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO
within its frequency range while the PLL is providing the desired output frequency.
The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock.
Since the minimum output divider value is 2, it is insured that the PLL output has a
50% duty cycle.The PLL is turned off and bypassed following a chip Reset and may
be enabled by software. The program must configure and activate the PLL, wait for
the PLL to Lock, then connect to the PLL as a clock source.
Reset has two sources on the LPC2119/LPC2129: the RESET pin and Watchdog
Reset. The RESET pin is a Schmitt trigger input pin with an additional glitch filter.
Assertion of chip Reset by any source starts the Wake-up Timer (see Wake-up Timer
description below), causing the internal chip reset to remain asserted until the
external Reset is de-asserted, the oscillator is running, a fixed number of clocks have
passed, and the on-chip Flash controller has completed its initialization.
When the internal Reset is removed, the processor begins executing at address 0,
which is the Reset vector. At that point, all of the processor and peripheral registers
have been initialized to predetermined values.
The wake-up timer ensures that the oscillator and other analog functions required for
chip operation are fully functional before the processor is allowed to execute
instructions. This is important at power on, all types of Reset, and whenever any of
the aforementioned functions are turned off for any reason. Since the oscillator and
other functions are turned off during Power-down mode, any wake-up of the
processor from Power-down mode makes use of the Wake-up Timer.
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Double edge controlled PWM outputs can be programmed to be either positive
going or negative going pulses.
Match register updates are synchronized with pulse outputs to prevent generation
of erroneous pulses. Software must ‘release’ new match values before they can
become effective.
May be used as a standard timer if the PWM mode is not enabled.
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
Rev. 02 — 02 February 2004
osc
and the ARM processor clock frequency is referred to
Section 6.20.2 “PLL”
osc
Single-chip 16/32-bit microcontrollers
LPC2119/LPC2129
and cclk are the same value unless
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
for additional
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