AD1836 Analog Devices, AD1836 Datasheet - Page 17

• Manufacturer Part Number: AD1836
• Description: Multi-channel 96kHz Codec
• Manufacturer: Analog Devices

REV. PrC
ADC Control Register 3
Address
15, 14, 13, 12
1110
ADC Peak Level Data Registers
Address
15, 14, 13, 12
1000 = ADC0
1001 = ADC1
1010 = ADC2
1011 = ADC3
When changing clock doubler bypass mode, other SPI bits that are written during the same SPI transaction may be lost. It is therefore recommended that a separate
transaction be used for setting CLKDBL Bypass Mode.
INPUT #1
INPUT #2
NOTE
ADC2 SINGLE-ENDED MUX PGA INPUT MODE – LEFT CHANNEL ONLY SHOWN
CONTROL REGISTER 3 CONTENTS: 6 LSBS: SELECT INPUT #1: 11 1010
LEFT
LEFT
1nF
1nF
C1
C2
CAP2L
CAP1L
RD/WR
11
0
RD/WR
11
1
V
V
Reserved
10, 9, 8
000
REF
REF
+
+
–
–
AD1836
SELECT INPUT #2: 11 1111
Clock
Mode
7, 6
00 = 256 × f
01 = 512 × f
10 = 768 × f
250
250
PGA
RSVD
10
0
S
S
S
GAIN SELECT
POWER-DOWN
INPUT SELECT
ADC2L
Left Diff.
I/P Select
5
0 = Differential
PGA Mode.
1 = PGA/MUX
Peak Level Data (10 Bits)
6-Data Bits
9..4
000000 = 0.0 dBFS
000001 = –1.0 dBFS
000010 = –2.0 dBFS
000011 = –3.0 dBFS
.
.
.
111111 = –63 dBFS
LEFT – VE
LEFT + VE
Right Diff.
I/P Select
4
0 = Differential
PGA Mode.
1 = PGA/MUX
Mode (Single-
Ended Input)
INPUT
INPUT
NOTE
ADC2 DIFFERENTIAL PGA INPUT MODE – LEFT CHANNEL ONLY SHOWN
CONTROL REGISTER 3 CONTENTS: 6 LSBS: 00 1010
1nF
1nF
C1
C2
CAP1L
CAP2L
Left
MUX/PGA
Enable
3
0 = Direct
1 = MUX/
PGA
Mode (Single-
Ended Input)
V
REF
–
+
+
–
Left
MUX
I/P Select
2
0 = I/P 0
1 = I/P 1
4-Fixed Bits
3..0
0000
The four LSBs are always zero.
AD1836
Function
250
250
Right
MUX/PGA
Enable
1
0 = Direct
1 = MUX/
PGA
AD1836
POWER-DOWN
GAIN SELECT
ADC2L
Right
MUX
I/P Select
0
0 = I/P 0
1 = I/P 1