AD1836 Analog Devices, AD1836 Datasheet - Page 8

• Manufacturer Part Number: AD1836
• Description: Multi-channel 96kHz Codec
• Manufacturer: Analog Devices

AD1836
FUNCTIONAL OVERVIEW
ADCs
There are four ADC channels in the AD1836, configured as two
independent stereo pairs. One stereo pair is the primary ADC and
has fully differential inputs. The second pair can be programmed
to operate in one of three possible input modes (programmed
via SPI ADC Control Register 3). The ADC section may also
operate at a sample rate of 96 kHz, with only the two primary
channels active. The ADCs include an on-board digital decima-
tion filter with 120 dB stopband attenuation and linear phase
response, operating at an oversampling ratio of 128 (for 4-channel
48 kHz operation) or 64 (for two-channel 96 kHz operation).
The primary ADC pair should be driven from a differential
signal source for best performance. The input pins of the pri-
mary ADC connect directly to internal switched capacitors. To
isolate the external driving op amp from the “glitches” caused
by the internal switched-capacitors, each input pin should be
isolated by using a series-connected external 100 Ω resistor
together with a 1 nF capacitor connected from each input to
ground. This capacitor must be of high quality; for example,
ceramic NPO or polypropylene film.
The secondary input pair can be operated in one of the follow-
ing three modes:
1. Direct differential inputs (driven the same as the primary
2. PGA mode with differential inputs (Figure 13). In this mode,
3. Single-ended MUX/PGA mode. In this mode, two single-
ADC inputs described above).
the PGA amplifier can be programmed using the SPI port to
give an input gain of 0 to 12 dB in 3 dB steps. External
capacitors are used after the PGA to supply filtering for the
switched-capacitor inputs.
ended stereo inputs are provided that can be selected using
the SPI port. Input gain can be programmed from 0 dB to
12 dB in steps of 3 dB External capacitors are used to supply
filtering for the switched-capacitor inputs.
OUTR2
OUTR3
OUTR1
OUTL2
OUTL3
OUTL1
A
A
CAPR
FILTR
A
CAPL
A
IN
IN
IN
IN
1R
2R
2L
1L
V
DAC 1
DAC 2
DAC 3
REF
L/R
L/R
L/R
AGND
AVDD
4
PGA
2
L/R
INTERPOLATION
INTERPOLATION
INTERPOLATION
FILTD
AD1836
FILTER
FILTER
FILTER
ADC2L/R
ADCI L/R
48/96kHz
48/96kHz
(MAX)
DVDD
DECIMATION
DECIMATION
48kHz (MAX)
2
CONTROL
CONTROL
CONTROL
48/96kHz
VOLUME
VOLUME
VOLUME
FILTER
FILTER
ADC peak level information for each ADC may be read from
the SPI port through Registers 12 through 15. The data is sup-
plied as a 10-bit word with a maximum range of 0 dB to –60 dB
and a resolution of 1 dB. The registers will hold peak informa-
tion until read; after reading, the registers are reset so that new
peak information can be acquired. Refer to the register descrip-
tion for details of the format.
The voltage at the V
bias external op amps used to buffer the input signals. This
source can be connected directly to op amp inputs but should
be buffered if it is required to drive resistive networks.
DACs
The AD1836 has six DAC channels arranged as three indepen-
dent stereo pairs, with six fully differential analog outputs for
improved noise and distortion performance. Each channel has
its own independently programmable attenuator, adjustable in
1024 linear steps. Digital inputs are supplied through three
serial data input pins (one for each stereo pair) and a common
frame (DLRCLK) and bit (DBLCK) clock. Alternatively, one
of the “packed data” modes may be used to access all six chan-
nels on a single TDM data pin.
Each set of differential output pins sits at a dc level of V
swings ± 1.4 V for a 0 dB digital input signal. A single op amp
third-order external low-pass filter is recommended to remove
high-frequency noise present on the output pins, as well as to
provide differential-to-single-ended conversion. A recommended
circuit is shown in Figure 2. Note that the use of op amps with
low slew rate or low bandwidth may cause high-frequency noise
and tones to fold down into the audio band; care should be
exercised in selecting these components.
The FILTD pin should be connected to an external grounded
capacitor. This pin is used to reduce the noise of the internal
DAC bias circuitry, thereby reducing the DAC output noise. In
some cases this capacitor may be eliminated with little effect on
performance. The voltage at the V
be used to bias external op amps used to buffer the output signals.
DGND
2
INTERFACE
INTERFACE
CONTROL
ODVDD
SERIAL
SERIAL
PORT
ADC
DAC
SPI
1
REF
pin, FILTR (~2.25 V) can be used to
SDOUT1
SDOUT2
ABCLK
ALRCLK
MCLK
DLRCLK
DBCLK
SDIN1
SDIN2
SDIN3
RESET
CCLK
CLATCH
CDATA
COUT
REF
pin, FILTR (~2.25 V) can
REF
REV. PrC
, and