AD1985 Analog Devices, AD1985 Datasheet - Page 28

• Manufacturer Part Number: AD1985
• Description: AC'97 2.3 Soundmax Codec W/jack Sensing
• Manufacturer: Analog Devices

Reg
Num
0x2A Extended
AD1985
Extended Audio Status and Control Register (Index 0x2A)
The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended audio features.
ASCVRA
ASCDRA
ASCSPDF
SPSA[1,0]
ASCCDAC
ASCSDAC
ASCLDAC
SPCV
PRI
PRJ
PRK
VFORCE
Name
Audio
Stat/Ctrl
D15
VFORCE X
D14 D13 D12 D11 D10 D9 D8
Variable Rate Audio. (Read/write.)
ASCVRA = 0 sets Fixed Sample Rate Audio at 48 kHz (reset default).
ASCVRA = 1 enables Variable Rate Audio mode (enables Sample Rate Registers and AC ’97 SLOTREQ Signaling).
Double Rate Audio.
ASCDRA = 1 enables Double-Rate Audio mode in which data from PCM L and PCM R in output slots 3 and 4 is used
in conjunction with PCM L (n+1) and PCM R (n+1) data to provide DAC streams at twice the sample rate designated
by the PCM Front Sample Rate Control Register.
When using the Double Rate audio only the Front DACs are supported, and all other DACs (Surround, Center and
LFE) are automatically powered down.
Note that ASCDRA can be used without ASCVRA; in that case the converter rates are forced to 96 kHz if ASCDRA = 1.
SPDIF Transmitter Subsystem Enable/Disable Bit. (Read/write.)
ASCSPDF = 1 enables the SPDIF transmitter.
ASCSPDF = 0 disables the SPDIF transmitter (default).
This bit is also used to validate that the SPDIF transmitter output is actually enabled.
The ASCSPDF bit is only allowed to be set high if the SPDIF pin (48) is pulled down at power-up, enabling the codec
transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled, and
therefore the ASCSPDF bit returns a low, indicating that the SPDIF transmitter is not available. This bit must always
be read back, to verify that the SPDIF transmitter is actually enabled.
SPDIF Slot Assignment Bits. (Read/write.)
These bits control the SPDIF slot assignment and respective defaults, depending on the codec ID configuration.
(See following table.)
Center DAC Status. (Read-only.)
ASCCDAC = 1 Indicates the PCM Center DAC is ready.
Surround DAC Status. (Read-only.)
ASCSDAC = 1 Indicates the PCM Surround DACs are ready.
LFE DAC Status. (Read-only.)
ASCLDAC = 1 Indicates the PCM LFE DAC is ready.
SPDIF Configuration Valid. (Read-only.) Indicates the status of the SPDIF transmitter subsystem, enabling the driver
to determine if the currently programmed SPDIF configuration is supported. SPCV is always valid, independent of
the SPDIF enable bit status.
SPCV = 0 indicates current SPDIF configuraton (SPSA, SPSR, DAC slot rate, DRS) is not valid (not supported).
SPCV = 1 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is valid (is supported).
Center DAC Power-Down. (Read/write.)
PRI = 1 mutes the PCM Center DAC. Essentially, PRI + PRK = powered off Center/LFE DACs.
Surround DACs Power-Down. (Read/write.)
PRJ = 1 turns off the PCM Surround DACs.
LFE DAC Power-Down. (Read/write.)
PRK = 1 mutes the PCM LFE DAC. Essentially, PRI + PRK = powered off Center/LFE DACs.
Validity Force Bit. (Reset default = 0.)
When asserted, this bit forces the SPDIF stream “Validity” flag (Bit <28> within each SPDIF L/R subframe) to be
controlled by the “V” bit (D15) in Register 0x3A (SPDIF control register).
VFORCE = 0 and “V” = 0: The “Validity” bit is managed by the codec error detection logic.
VFORCE = 0 and “V” = 1: The “Validity” bit is forced high, indicating subframe data is invalid.
VFORCE = 1 and “V” = 0: The “Validity” bit is forced low, indicating subframe data is valid.
VFORCE = 1 and “V” = 1: The “Validity” bit is forced high, indicating subframe data is invalid.
PRK PRJ PRI SPCV X ASCLDAC ASCSDAC ASCCDAC SPSA1 SPSA0 X ASCSPDF ASCDRA ASCVRA 0xXXXX
Rev. 0 | Page 28 of 48
D7
D6
D5
D4
D3 D2
D1
D0
Default