ADSP-21061 Analog Devices, ADSP-21061 Datasheet - Page 39

• Manufacturer Part Number: ADSP-21061
• Description: ADSP-2106x SHARC DSP Microcomputer Family
• Manufacturer: Analog Devices

Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
to be the difference between the ADSP-2106x’s output voltage
and the input threshold for the device requiring the hold time. A
typical ∆V will be 0.4 V. C
data line), and I
data line). The hold time will be t
disable time (i.e., t
REFERENCE
V
V
OH (MEASURED)
OL (MEASURED)
OUTPUT
SIGNAL
OUTPUT
t
DIS
OUTPUT STOPS
DECAY
PIN
L
TO
DRIVING
is the total leakage or three-state current (per
DATRWH
50pF
using the equation given above. Choose ∆V
t
MEASURED
V
V
OH (MEASURED)
OL (MEASURED)
t
DECAY
L
for the write cycle).
is the total bus capacitance (per
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
DECAY
I
I
OH
OL
+ V
– V
plus the minimum
OUTPUT STARTS
t
ENA
1.0V
2.0V
DRIVING
+1.5V
V
V
OH (MEASURED)
OL (MEASURED)
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 25). The delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figures 28–29,
32–33 show how output rise time varies with capacitance. Fig-
ures 30, 34 show graphically how output delays and holds vary
with load capacitance. (Note that this graph or derating does
not apply to output disable delays; see the previous section
Output Disable Time under Test Conditions.) The graphs of
Figures 28, 29 and 30 may not be linear outside the ranges
shown.
INPUT OR
OUTPUT
ADSP-21061/ADSP-21061L
1.5V
1.5V