ADSP-TS101S Analog Devices, ADSP-TS101S Datasheet - Page 33

• Manufacturer Part Number: ADSP-TS101S
• Description: Embedded Processor
• Manufacturer: Analog Devices

The output enable time t
t
t
switches to when the output voltage ramps V from the measured
three-stated output level. The t
load C
Capacitive Loading
Output valid and hold are based on standard capacitive loads:
30 pF on all pins (see
tions given should be derated by a drive strength related factor
for loads other than the nominal value of 30 pF.
through
itance.
load capacitance. (Note that this graph or derating does not apply
to output disable delays; see
The graphs of
outside the ranges shown.
REV. A
MEASURED_ENA
MEASURED_ENA
Figure 25. Typical Output Rise and Fall Time (10%–90%,
V
DD_IO
L
Figure 24. Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
Figure 33
, drive current I
25
20
15
10
5
0
Figure 32
= 3.3 V) vs. Load Capacitance at Strength 0
0
and t
is the interval from when the reference signal
y = 0.2015x + 3.8869
10
Figure 25
OUTPUT
PIN
TO
RISE TIME
graphically shows how output valid varies with
20
RAMP
show how output rise time varies with capac-
Figure
30
as shown in
D
LOAD CAPACITANCE – pF
, and with V equal to 0.5 V.
ENA
through
(V
40
STRENGTH 0
Output Disable Time on Page
DD_IO
is the difference between
24). The delay and hold specifica-
30pF
RAMP
50
= 3.3V)
Figure 33
Figure
value is calculated with test
50
60
70
y = 0.174x + 2.6931
23. The time
may not be linear
1.5V
FALL TIME
80
Figure 25
90
100
32.)
–33–
Figure 26. Typical Output Rise and Fall Time (10%–90%,
V
Figure 27. Typical Output Rise and Fall Time (10%–90%,
V
Figure 28. Typical Output Rise and Fall Time (10%–90%,
V
DD_IO
DD_IO
DD_IO
25
20
15
10
25
20
15
10
25
20
15
10
5
0
5
0
5
0
= 3.3 V) vs. Load Capacitance at Strength 1
= 3.3 V) vs. Load Capacitance at Strength 2
= 3.3 V) vs. Load Capacitance at Strength 3
0
0
0
y = 0.1082x + 1.3123
y = 0.1349x + 1.9955
y = 0.1304x + 0.8427
10
10
10
RISE TIME
RISE TIME
RISE TIME
20
20
20
30
30
30
LOAD CAPACITANCE – pF
LOAD CAPACITANCE – pF
LOAD CAPACITANCE – pF
(V
(V
40
40
(V
STRENGTH 2
STRENGTH 1
40
STRENGTH 3
DD_IO
DD_IO
DD_IO
50
50
50
= 3.3V)
= 3.3V)
= 3.3V)
ADSP-TS101S
60
60
60
70
70
70
y = 0.1144x + 0.7025
y = 0.1163x + 1.4058
y = 0.0912x + 1.2048
FALL TIME
80
80
80
FALL TIME
FALL TIME
90
90
90
100
100
100