AN123 Silicon_Laboratories, AN123 Datasheet

AN123

Manufacturer Part Number

AN123

Description

Using THE DAC AS A Function Generator

Manufacturer

Silicon_Laboratories

Datasheet

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Relevant Devices

This application note applies to the following devices:

C8051F020, C8051F021, C8051F022, and

C8051F023.

Introduction

This document describes how to implement an

interrupt driven multifunction generator on C8051

devices using the on-chip digital-to-analog con-

verter (DAC).

Features

•

Key Points

•

Rev. 1.1 12/03

S I N G T H E

Four different waveforms expandable to any

periodic function defined in a table.

- Sine Wave (Table Defined)

- Square Wave (Calculated)

- Triangle Wave (Calculated)

- Saw Tooth Wave (Calculated)

Allows selection of the frequency and ampli-

tude of waveform at run time.

An interactive interface with a PC using the

serial communications port and HyperTerminal

or an equivalent program.

Output waveforms have 16-bit frequency reso-

lution using the phase accumulator approach.

The on-chip DAC’s can support waveform gen-

eration up to 50 kHz.

By using a 16-bit lookup table with a 12-bit

DAC, error in the amplitude is virtually elimi-

nated.

D A C

A S A

U N C T I O N

Implementation

The main routine of this program is a command

interpreter that sets parameters for the Timer 4

interrupt service routine (ISR) which manages the

DAC updates. The Timer 4 interrupts occur at a

predetermined rate set at compile time. In the

included software example, this value is stored in

the

Timer 4 ISR updates the DAC and calculates or

looks up the next output value based on the wave-

form settings.

Setting up the DAC

Any free DAC, referred to as DACn, may be used

to generate waveforms. In this example DACn is

used in left-justified mode with output scheduling

based on Timer 4 overflows. Refer to the data sheet

for specific information on how to set the DAC-

nCN register to specify DACn modes.

When the DAC is configured to left-justified mode,

16-bit data can be written to the 12-bit data register

with no shifting required. In this case, the 4 least

significant bits are ignored.

In this example, DACn updates occur on Timer 4

overflows, meaning writes to DACnH and DACnL

have no immediate effect on the DAC output, but

instead are held until the next Timer 4 overflow.

Another important note is that the internal voltage

reference must be enabled by setting the appropri-

ate bits in the REFnCN register before the DAC

can be used.

Sampling Rate

The sampling rate is configured by initializing the

Timer 4 reload value with the number of SYSCLK

constant

E N E R A T O R

<SAMPLE_RATE_DAC>.

AN123

AN123-DS11

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