AN123 Silicon_Laboratories, AN123 Datasheet - Page 2

• Manufacturer Part Number: AN123
• Description: Using THE DAC AS A Function Generator
• Manufacturer: Silicon_Laboratories

AN123
cycles between interrupts. This number is negative
because C8051 timers are up-counters and can be
calculated using the following formula:
The maximum sampling rate allowed by the DAC
is approximately 100 kHz, given by the 10 µs out-
put settling time. However, use caution when
selecting the DAC sampling rate because all
instructions in the longest path of the ISR must be
executed before the next Timer 4 interrupt, or the
output frequency will be affected. For example,
using a SYSCLK of 22.1 MHz and a DAC update
rate of 80 kHz allows 276 SYSCLK cycles for the
ISR to finish execution. The main trade-off is
between the sampling rate and the execution time
of the Timer 4 ISR. One way execution time of the
ISR can be reduced to achieve a higher sampling
rate is by removing the gain adjustment stage. Also
note that the maximum output frequency is limited
to no more than one half the sampling rate (Nyquist
theorem).
Waveform Generation
Waveform generation occurs entirely in the
Timer 4 ISR and is implemented in three stages.
The 2D playing field, shown in Figure 1, is used to
define one period of any periodic function. It has
two 16-bit axes, a horizontal phase axis ranging
2
32767
-32768
0
Timer 4 Reload
Figure 1. One Period of a Table Defined Sine Wave
=
16384
---------------------------------------------------------- -
SAMPLE_RATE_DAC
64
– (
SYSCLK
)
32767
128
Rev. 1.1
from 0 to 65535, and a vertical 2’s complement
amplitude axis ranging from -32768 to 32767.
All waveforms generated use a 16-bit phase accu-
mulator which keeps track of where the output
waveform is on the horizontal axis. This phase
accumulator provides a frequency resolution of
1.2 Hz, given a DAC update rate of 80 kHz. Based
on waveform settings, the first stage of Timer 4
ISR either calculates or looks up the next DAC out-
put level corresponding to the phase accumulator.
The phase accumulator is incremented by the vari-
able <phase_add> every time the Timer 4 ISR is
called. The magnitude of <phase_add> is deter-
mined by the desired output frequency based on
this formula:
The entries in the lookup table and the results of the
initial calculations are full-scale values. The second
stage of the Timer 4 ISR scales the output level
according to the <amplitude> parameter specified
at the command prompt.
The final processing stage converts the scaled
2’s complement value to an unsigned unipolar
value prior to delivery to the DAC. This is accom-
plished by adding 32768 to the 2’s complement
49152
where PHASE_PRECISION = 65536
phase_add
192
=
frequency
65535
255
×
---------------------------------------------------------- -
SAMPLE_RATE_DAC
PHASE_PRECISION
16-bit phase axis
8-bit table index