WM8955BL Wolfson Microelectronics, WM8955BL Datasheet - Page 12

• Manufacturer Part Number: WM8955BL
• Description: Stereo DAC
• Manufacturer: Wolfson Microelectronics

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WM8955BL
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
AUDIO INTERFACE TIMING – MASTER MODE
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
Test Conditions
CLKDIV2 = 0, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T
unless otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
MCLK duty cycle
Test Conditions
CLKDIV2 = 1, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T
unless otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
Test Conditions
DBVDD = 3.3V, DGND = 0V, T
PARAMETER
Bit Clock Timing Information
BCLK rise time (10pF load)
BCLK fall time (10pF load)
BCLK duty cycle (normal mode, BCLK =
MCLK/n)
BCLK duty cycle (USB mode, BCLK = MCLK)
DACLRC
DACDAT
(Output)
(Output)
BCLK
Figure 1 System Clock Timing Requirements
A
MCLK
= +25
o
C, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
t
DST
SYMBOL
SYMBOL
T
T
T
T
T
T
T
MCLKDS
MCLKL
MCLKH
MCLKY
MCLKL
MCLKH
MCLKY
SYMBOL
t
t
t
t
BCLKDS
BCLKDS
BCLKR
BCLKF
t
A
A
MCLKL
= +25
= +25
t
MCLKY
t
DHT
o
o
t
MCLKH
C, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,
C, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,
t
DL
60:40
MIN
MIN
MIN
21
21
54
10
10
27
T
50:50
TYP
TYP
TYP
MCLKDS
PD Rev 4.1 February 2007
40:60
MAX
MAX
MAX
3
3
Production Data
UNIT
UNIT
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
12