WM8955BL Wolfson Microelectronics, WM8955BL Datasheet - Page 29

• Manufacturer Part Number: WM8955BL
• Description: Stereo DAC
• Manufacturer: Wolfson Microelectronics

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Production Data
MASTER CLOCK AND PHASE LOCKED LOOP
Figure 17 PLL Circuit
MCLK
f/2
The WM8955BL has an on-chip phase-locked loop (PLL) circuit that can be used to:
•
The PLL circuit is shown below.
Table 19 PLL and Clocking Control
MCLK
DIV2
R8 (08h)
Sample Rates
R43 (2Bh)
Clocking and
PLL
f
REGISTER
ADDRESS
1
generate a master clock for the WM8955BL audio function from another external clock,
e.g. in telecoms applications.
R = f
PLL
2
/ f
1
BIT
6
8
5
4
3
f
2
f/4
MCLKDIV2
MCLKSEL
PLLOUTDIV2
PLL_RB
PLLEN
LABEL
f/2
DEFAULT
PLLOUT
0
0
0
0
0
DIV2
MCLK Divide by 2
0: Divide disabled
1: Divide enabled
Select internal master clock
0: from MCLK pin
1: from PLL (make sure PLLEN=1)
PLL Output Divide by 2
0: Divide disabled
1: Divide enabled
0: PLL held in reset
1: PLL running (if PLLEN=1)
PLL Enable
0: PLL disabled; 1: PLL enabled.
MCLK
SEL
DESCRIPTION
PD Rev 4.1 February 2007
WM8955BL
DIGITAL
CORE
29