AMBE-1000 Digital Voice Systems, Inc., AMBE-1000 Datasheet - Page 28

• Manufacturer Part Number: AMBE-1000
• Manufacturer: Digital Voice Systems, Inc.

CHS_O_STRB
CHS_I_STRB
CHS_O_CLK
CHS_I_CLK
CHS_SYNC
CHS_OBE
CHS_IBF
CHS_DO
CHS_DI
Symbol
EPR
DPE
Pin
The AMBE-1000 is not recommended for new designs.
Please refer to the AMBE-2000/2020 product line.
Table 3-G Channel Serial Interface Pin Descriptions
(see Table
Selectable
Direction
In/Out
3-A)
Out
Out
Out
Out
Out
Out
Pin
In
In
In
In
The AMBE-1000 is not recommended for new designs.
Please refer to the AMBE-2000/2020 product line.
Number
Pin
46
47
59
60
65
63
68
69
64
61
67
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Description
Encoder Packet Ready : This output signal will go high once every 20
milliseconds to indicate that the encoder has a frame of data to output. It
will return low some time after the first CHS_O_STRB.
Decoder Packet Empty : This output signal will go high once every 20
milliseconds to indicate that the decoder is ready to accept another frame of
data. It will return low some time after the first CHS_I_STRB.
Serial Data Input : 16 bits of channel data are input on CHS_DI,
synchronous to CHS_I_CLK, with each CHS_I_STRB pulse.
Serial Input Clock : In coordination with CHS_I_STRB, CHS_DI is latched
by the AMBE-1000™ on the rising edges of CHS_I_CLK. In active mode
this input pin should be connected to CHS_O_CLK, which is running at
CLK_I
CLK_I
Input (Write) Data Strobe : This signal indicates to the AMBE-1000™
when the data on CHS_DI will be latched by CHS_I_CLK.
mode, following a falling edge of CHS_I_STRB, the MSB of CHS_DI will be
latched on the second rising edge of CHS_I_CLK. In active mode, following
a falling edge of CHS_I_STRB, the MSB of CHS_DI will be latched on the
first rising edge of CHS_I_CLK.
other 15 bits are latched on successive rising edges of CHS_I_CLK. In
active mode this signal should be tied to CHS_SYNC.
Input Buffer Full : This signal will go active high after each write
(CHS_I_STRB) to the serial port. The port is ready to be written to again
when this signal returns low.
time between CHS_I_STRB pulses is at least 350 cycles of the input clock,
CLK_I, at which time the input buffer is guaranteed to be empty again.
Serial Data Output : 16 bits of channel data are output on CHS_DO,
synchronous to CHS_O_CLK, with each CHS_O_STRB pulse.
Serial Output Clock : In coordination with CHS_O_STRB, the data on
CHS_DO is output by the AMBE-1000™ on the rising edges of CHS_O_CLK.
In active mode this output pin is running at CLK_I
maximum frequency for this signal is CLK_I
Output (Read) Data Strobe : This signal indicates to the AMBE-1000™
when to bring the data to the CHS_DO pin.
CHS_O_STRB, the MSB of CHS_DO comes out on the first rising edge of
CHS_O_CLK, with the other 15 bits following on successive rising edges of
CHS_O_CLK. In active mode this signal should be tied to CHS_SYNC.
Serial Output Buffer Empty : This signal will go active high after each
read (CHS_O_STRB) of the serial port. The port is ready to be read again
when this signal returns low.
time between CHS_O_STRB pulses is at least 350 cycles of the input clock,
CLK_I, at which time the output buffer is guaranteed to be full again.
Serial Sync : This pin is only used in active mode as a source for
CHS_I_STRB and CHS_O_STRB.
inputs, and outputs the necessary 17 strobe pulses each of which is 64
cycles of CHS_O_CLK in length. See Figure 3-K. In passive mode this pin
is left unconnected.
page 28
2.
6.
In passive mode the maximum frequency for this signal is
CHS_OBE can effectively be ignored if the
CHS_IBF can effectively be ignored if the
In both active and passive modes, the
This signal is tied to these two strobe
2.
Following a falling edge of
6. In passive mode the
In passive