MT55L128L18F1 Micron Semiconductor Products, Inc., MT55L128L18F1 Datasheet
MT55L128L18F1
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MT55L128L18F1 Summary of contents
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... Temperature Commercial (0°C to +70°C) Part Number Example: MT55L128L18F1T-10 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_C.p65 – Rev. C, Pub. 11/02 PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM MT55L128L18F1, MT55L64L32F1, MT55L64L36F1 3 ...
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... CE2 CE2# NOTE: Functional Block Diagrams illustrate simplified device operation. See Truth Table, Pin Descriptions and timing diagrams for detailed information. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, FLOW-THROUGH ZBT SRAM FUNCTIONAL BLOCK DIAGRAM 128K ...
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... DQd 50 * Pins 50, 83, and 84 are reserved for address expansion. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles ...
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... for x32 version, DQPx for x36 version. ** Pins 50, 83 and 84 are reserved for address expansion. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, FLOW-THROUGH ZBT SRAM PIN ASSIGNMENT (Top View) 100-Pin TQFP ...
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... I/O, Flow-Through ZBT SRAM MT55L128L18F1_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM SYMBOL TYPE SA0 Input Synchronous Address Inputs: These inputs are SA1 registered and must meet the setup and hold times S A around the rising edge of CLK ...
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... I/O, Flow-Through ZBT SRAM MT55L128L18F1_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM SYMBOL TYPE R/W# Input Read/Write: This input determines the cycle type when ADV/LD# is LOW and is the only means for determining READs and WRITEs ...
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... WRITE Byte “c” WRITE Byte “d” WRITE All Bytes WRITE ABORT/NOP NOTE: Using R/W# and byte write(s), any one or more bytes may be written. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, FLOW-THROUGH ZBT SRAM THIRD ADDRESS (INTERNAL) X...X01 X...X00 X...X11 X ...
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... NOTE STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the clock (CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock (CLK). 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, FLOW-THROUGH ZBT SRAM State Diagram for ZBT SRAM DS ...
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... The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST cycle. 11. The address counter is incremented for all CONTINUE BURST cycles. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, FLOW-THROUGH ZBT SRAM ADDRESS CE# CE2# CE2 ZZ ADV/ R/W# BWx OE# CKE# CLK ...
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... V Q should never exceed This parameter is sampled. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, FLOW-THROUGH ZBT SRAM *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to .... -0.5V to +4.6V SS the device ...
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... Typical values are measured at 3.3V, 25°C, and 12ns cycle time. 4. This parameter is sampled. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, FLOW-THROUGH ZBT SRAM CONDITIONS ≥ ...
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... A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, FLOW-THROUGH ZBT SRAM , +3.3V ± ...
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... SRAM timing is dependent upon the capacitive load- ing on the outputs. Consult the factory for copies of I/O current versus voltage curves. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM Output Load Equivalents to 3.0V SS ...
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... SUPPLY I ISB2Z ALL INPUTS (except ZZ) Outputs (Q) 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, FLOW-THROUGH ZBT SRAM the ZZ pin becomes a logic HIGH, I after the time tion pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pend- ing operations are completed ...
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... Data coherency is provided for all possible operations READ is initiated, the most current data is used. The most recent data may be from the input data register. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, FLOW-THROUGH ZBT SRAM READ/WRITE TIMING ...
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... Data coherency is provided for all possible operations READ is initiated, the most current data is used. The most recent data may be from the input data register. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, FLOW-THROUGH ZBT SRAM NOP, STALL AND DESELECT CYCLES ...
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... ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by Micron Technology, Inc., and Motorola Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, FLOW-THROUGH ZBT SRAM 100-PIN PLASTIC TQFP (JEDEC LQFP) 0.625 14.00 ± ...
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... Changed heading on Mechanical Drawing from BGA to FBGA Added 165-Pin FBGA package, REV 5/00, FINAL ................................................................................................. May/23/00 Added PRELIMINARY PACKAGE DATA to diagram 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM MT55L128L18F1_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...