MT90401 Zarlink Semiconductor, MT90401 Datasheet - Page 22

• Manufacturer Part Number: MT90401
• Description: Sonet/sdh System Synchronizer
• Manufacturer: Zarlink Semiconductor

3.6
Also referred to as pull-in range. This is the input frequency range over which the synchronizer must be able to pull
into synchronization. The MT90401 capture range is equal to
(C20i). For example, a 32 ppm master clock results in a capture range of 20 ppm.
In Telcordia GR-1244-CORE, it is a conditional requirement that the PLL should be able to reject references that
are off the nominal frequency by more than 17ppm. MT90401 provides two pins and two bits, PRIOOR and
SECOOR, to indicate whether the primary and secondary reference are within the 17ppm of the nominal frequency.
When the accuracy of the 20MHz oscillator is 4.6ppm the effective out of range limits of the PRIOOR and SECOOR
pins will be +16.6ppm to -7.4ppm or +7.4ppm to -16.6ppm. Both references are monitored at the same time.
PRIOOR and SECOOR are updated every 1.0 to 1.5 seconds.
3.7
This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock
range is equal to the capture range for the MT90401.
3.8
Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect
to an ideal signal. The given signal is typically the output signal. An ideal signal is one that is at exactly the nominal
frequency and is completely free of jitter and wander.
3.9
Frequency slope is measured in ppm per second and is the rate at which the fractional frequency offset of a given
signal changes. The fractional frequency offset is calculated with respect to an ideal signal. The given signal is
typically the output signal. An ideal signal is one that is at exactly the nominal frequency and is completely free of
jitter and wander.
3.10
TIE is the time delay between a given timing signal and an ideal timing signal.
3.11
MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a
particular observation period.
3.12
Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a
particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency.
Phase continuity applies to the output of the synchronizer after a signal disturbance due to a reference switch or a
mode change.
Capture Range
Lock Range
Phase Slope
Frequency Slope
Maximum Time Interval Error (MTIE)
Time Interval Error (TIE)
Phase Continuity
MTIE S
=
TIEmax t
Zarlink Semiconductor Inc.
MT90401
22
–
TIEmin t
52 ppm minus the accuracy of the master clock
Data Sheet