MT90401 Zarlink Semiconductor, MT90401 Datasheet - Page 23

• Manufacturer Part Number: MT90401
• Description: Sonet/sdh System Synchronizer
• Manufacturer: Zarlink Semiconductor

3.13
This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal
and output signal are not changing in phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is affected by many factors which include:
1. initial input to output phase difference
2. initial input to output frequency difference
3. synchronizer loop filter
4. synchronizer limiter
Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time. And better (smaller) phase slope performance (limiter) results in longer lock times. The MT90401 loop filter
and limiter were optimized to meet the GR-253-CORE, GR-1244-CORE, and G-813 jitter transfer and phase slope
requirements.
4.0
The MT90401 meets all applicable PLL requirements for the following specifications.
1. Telcordia GR-1244-CORE December 2000 for Stratum 3, SONET Minimum Clock (SMC), Stratum 4 Enhanced
2. Telcordia GR-253-CORE September 2000 for SONET Internal Clocks
3. ANSI T1.101 (DS1) February 1994 for Stratum 3, Stratum 4 Enhanced and Stratum 4
4. ANSI T1.105.09-1996 for SONET Minimum Clocks (SMCs)
5. ITU-T G.813 August 1996 for Option1 and Option 2 clocks (with external jitter attenuator)
5.0
This section contains MT90401 application specific details for Master clock operation, LVDS output drivers setup,
microport functionality and output clock phase adjustment.
5.1
In Freerun Mode, the frequency tolerance at the clock outputs is identical to the frequency tolerance of the source
at the C20i input pin.
Another consideration in determining the accuracy of the master timing source is the desired capture range. The
sum of the accuracy of the master timing source and the capture range of the MT90401 will always equal 52ppm.
For example, if the master timing source is 20 ppm, then the capture range will be 32 ppm.
5.2
When Primary Holdover Mode is entered for short time periods, TIE correction should not be enabled. This will
prevent unwanted accumulated phase change between the input and output.
For example, we can estimate phase accumulation for a case when ten Normal to Holdover to Normal sequential
mode changes occur, with each Holdover entered for 2s with TIE enabled. Each mode change could account for a
phase shift as large as 250ns. Thus, the accumulated phase could be as large as 2.9us, and, the overall MTIE
could be as large as 2.9us.
and Stratum 4
Master Clock
TIE Correction (using PCCi)
MT90401 and Network Specifications
Applications
Phase Lock Time
Zarlink Semiconductor Inc.
MT90401
23
Data Sheet