MT90401 Zarlink Semiconductor, MT90401 Datasheet - Page 5

• Manufacturer Part Number: MT90401
• Description: Sonet/sdh System Synchronizer
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
Pin #
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
HOLDOVER Holdover (CMOS Output). This output goes high when the device is in holdover mode.
SECOOR
C34/C44
FLOCK
Name
LOCK
RSEL
TCLR
PCCi
V
V
V
C20i
NC
OE
DS
IC
DD3
SS7
DD4
Reference Source Select (Input). A logic low selects the PRI (primary) reference source
as the input reference signal and a logic high selects the SEC (secondary) input. The logic
level at this input is gated in by the rising edge of F8o. For more details see RSEL bit
description in Table 6 - Control Register 1 (Address 00H - Read/Write).
TIE Circuit Clear (Input). A logic low at this input clears the Time Interval Error (TIE)
correction circuit resulting in a realignment of output phase with input phase. The TCLR pin
should be held low for a minimum of 300ns. When this pin is held low, the time interval error
correction circuit is disabled.
Positive Power Supply. Digital supply.
No Connection.
20 MHz Clock Input (5V tolerant Input). This pin is the input for the master 20MHz clock.
Digital ground. 0Volts
Controlled Clock 34.368MHz / Clock 44.736MHz (CMOS Output). This output clock is
programmable to be either 34.368MHz (for E3 applications) or 44.736MHz (for DS3
applications). The output clock is controlled via control pins in Hardware Mode or control
bits when the device is in Microport Mode.
If the E3DS3/OC3 control pin or control bit is high, the C34/C44 pin will output its nominal
frequency. If the E3DS3/OC3 control pin or bit is low, the C34/C44 pin will output its nominal
frequency divided by 4. (C8.5o/C11o)
Positive Power Supply. Digital supply.
Phase Continuity Control Input (3V Input). The signal at this pin affects the state changes
between Primary Holdover Mode and Primary Normal Mode and Primary Holdover Mode
and Secondary Normal Mode. The logic level at this input is gated by the rising edge of F8o.
See Figure 12, “Control State Diagram” on page 21 for details.
Lock Indicator (CMOS Output). This output goes high when the PLL is in frequency lock
to the input reference.
Fast Lock Mode (Input). In hardware mode, hold this pin high to lock faster than normal to
the input reference. This pin performs no function if the device is not in hardware mode. In
Fast Lock Mode, the wander generation of the PLL is, of necessity, compromised.
Data Strobe (5V tolerant Input). This input is the active low data strobe of the Motorola
processor interface.
Internal Connection. Tie low for normal operation.
Secondary Reference Out Of Capture Range (CMOS Output). A logic high at this pin
indicates that the secondary reference is off the PLL center frequency by more than 12
ppm. The measurement is done on a 1 second basis using a signal derived from the 20MHz
clock input on the C20i pin. When the accuracy of the 20MHz clock is
effective out of range limits of the SECOOR signal will be
to -16.6ppm.
Output Enable (Input). Tie high for normal operation. Tie low to force output clocks pins
F16, F8, C16, C8, C4, C2 to a high impedance state.
Zarlink Semiconductor Inc.
MT90401
5
Description
6.6ppm to -7.4ppm or +7.4ppm
Data Sheet
4.6ppm the