MT9123AE Zarlink Semiconductor, MT9123AE Datasheet - Page 18

• Manufacturer Part Number: MT9123AE
• Description: Description = Dual Voice Echo CANceller ( Itu-t G165 Compliant) ;; Package Type = Pdip ;; No. Of Pins = 28
• Manufacturer: Zarlink Semiconductor

MT9123
18
The Exponential Decay registers (Decay Step Number and Decay Step Size) and Flat Delay register allow the LMS adaptation
step-size (MU) to be programmed over the length of the FIR filter. A programmable MU profile allows the performance of the echo
canceller to be optimized for specific applications. For example, if the characteristic of the echo response is known to have a flat
delay of several milliseconds and a roughly exponential decay of the echo impulse response, then the MU profile can be
programmed to approximate this expected impulse response thereby improving the convergence characteristics of the adaptive
filter. Note that in the following register descriptions, one tap is equivalent to 125
FD
SSC
NS
Echo Canceller A, Flat Delay Register
Echo Canceller B, Flat Delay Register
FD
Echo Canceller A, Decay Step Number Register
Echo Canceller B, Decay Step Number Register
NS
Echo Canceller A, Decay Step Size Control Register
Echo Canceller B, Decay Step Size Control Register
SSC
7-0
7-0
2-0
Amplitude of MU
1.0
2
-16
as FD
range of FD
FD
decay rate is defined as a decrease of MU by a factor of 2 every SS taps of the FIR filter, where SS = 4 x2
example; If SSC
is 04h.
period of SS taps (see SSC
Filter Length (512 or 1024) - [ Decay Step Number (NS
For example, if NS
256 taps for a filter length of 512 taps.
Flat Delay: This register defines the flat delay of the MU profile, (i.e., where the MU value is 2
Decay Step Size Control: This register controls the step size (SS) to be used during the exponential decay of MU. The
Decay Step Number: This register defines the number of steps to be used for the decay of MU where each step has a
Note: Bits marked with “0” are reserved bits and should be written “0”.
7-0
NS
7-0
is zero.
FD
Flat Delay (FD
7
7
0
7
7
7
x 8 taps. For example; if FD
7-0
NS
is: 0 <= FD
FD
2-0
6
0
6
6
6
7-0
6
= 4, then MU is reduced by a factor of 2 every 64 taps of the FIR filter. The default value of SSC
7-0
=4 and SSC
)
NS
FD
7-0
5
5
2-0
0
5
5
5
<= 64 in normal mode and 0 <= FD
). The start of the exponential decay is defined as:
2-0
NS
=4, then the exponential decay start value is 512 - [NS
FD
4
4
4
0
FIR Filter Length (512 or 1024 taps)
7-0
4
4
= 5, then MU=2
NS
FD
3
0
3
3
3
3
NS
SSC
FD
2
7-0
-16
2
2
2
) x Step Size (SS) ] where SS = 4 x2
2
for the first 40 taps of the echo canceller FIR filter. The valid
2
7-0
NS
SSC
1
FD
1
1
<= 128 in extended-delay mode. The default value of
1
1
µ
1
s (64ms/512 taps).
ADDRESS = 04h WRITE/READ VERIFY
ADDRESS = 07h WRITE/READ VERIFY
ADDRESS = 24h WRITE/READ VERIFY
ADDRESS = 27h WRITE/READ VERIFY
ADDRESS = 06h WRITE/READ VERIFY
ADDRESS = 26h WRITE/READ VERIFY
NS
SSC
0
FD
0
0
0
Step Size (SS)
0
0
Number of Steps (NS
7-0
x SS] = 512 - [4 x (4x2
-16
SSC
). The delay is defined
Power Reset Value
Power Reset Value
Power Reset Value
2-0
.
00h
04h
Data Sheet
00h
7-0
SSC
Time
)
2-0
. For
4
)] =
2-0