MT8910-1 Mitel Networks Corporation, MT8910-1 Datasheet - Page 15

• Manufacturer Part Number: MT8910-1
• Description: CMOS St-bus Family Digital Subscriber Line Interface Circuit
• Manufacturer: Mitel Networks Corporation

Preliminary Information
Bits 5, 4 and 3 of Status Register 1, IS2, IS1 and
IS0, provide an indication of the internal state of the
device. The decoded states are as follows:
IS2
0
0
0
0
1
1
1
1
Bit 2 of Status Register 1, RxSFIB, is used to
indicate the reception of the receive superframe
boundary in both the LT and NT modes.
Bit 0 of Status Register 1, CRCERR, indicates the
state of the CRC check.
states that the CRC check calculated by the
MT8910-1 did not correspond to the CRC bits
received in the M-channel.
updated once every superframe.
Note 1) Not Production Tested
5,4,3,
Bit
7,6
2,1
0
IS1
0
0
1
1
0
0
1
1
SRID1, SRID0
SRID1
bit 7
QSNR4,
QSNR3,
QSNR2,
QSNR1,
QSNR0
IS0 Definition
0
1
0
1
0
1
0
1
Name
NA
Full Reset
Training with no sync
Training
Training with sync and superframe
Loss of sync
NA
Loss of superframe sync
Active
superframe sync
sync
SRID0
bit 6
Status Register ID. Always reads 0, 1, respectively, when Status Register 2 is output.
Quantizer Signal to Noise Ratio Bits. (see Note 1)
Reserved. Always reads 0.
QSNR4 (MSB) -
A logic high on this bit
QSNR0 (LSB)
with
This bit will only be
00000
00001
00010
00100
00101
01000
01001
01010
00011
00110
00111
01011
01100
01101
01110
01111
QSNR4
bit 5
sync
Table 6. Status Register 2
but
QSNR3
bit 4
no
QSNR (dB)
MEAN
>36.1
36.1
30.1
26.6
24.1
22.2
20.6
19.2
18.1
17.1
16.1
15.3
14.6
13.9
13.2
12.6
QSNR2
bit 3
Status Register 2
When SRID1=0 and SRID0=1, the contents of Status
Register 2 are being output in the C-channel allowing
the system to monitor the status of the quantizer
signal to noise ratio bits (refer to Table 6).
QSNR bits reflect the eye closure of the received
signal and represent the signal (+1 symbol) to noise
ratio at the input of the quantizer. This information
can be used to indicate the error performance of the
transceiver.
QSNR, these bits should be averaged over a period
of 64 ST-BUS frames (640 baud). The conversion of
the five bit output to QSNR is shown in Table 6. For
a bit error rate of greater than 10
QSNR should be greater than 15.7dB.
Status Register 3
When SRID1=1 and SRID0=0, the contents of Status
Register 3 are being output in the C-channel allowing
the system to monitor the mean level of the received
symbols (refer to Table 7).
Amplitude bits (RPA4 to RPA0) provide an estimate
of the attenuation of the loop. The representation of
the RPA bits is shown in Table 7.
Description
QSNR1
bit 2
QSNR4 (MSB) -
QSNR0 (LSB)
For a more accurate indication of
10000
10001
10010
10100
10101
10011
10110
11000
11001
11010
10111
11011
11100
11101
11110
11111
QSNR0
bit 1
The Received Pulse
MT8910-1
-7
bit 0
NA
, the theoretical
QSNR( dB)
MEAN
12.1
10.6
10.1
11.5
11.0
9.7
9.3
8.9
8.5
8.2
7.9
7.5
7.2
6.9
6.6
6.3
The
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