MT8910-1 Mitel Networks Corporation, MT8910-1 Datasheet - Page 17

• Manufacturer Part Number: MT8910-1
• Description: CMOS St-bus Family Digital Subscriber Line Interface Circuit
• Manufacturer: Mitel Networks Corporation

Preliminary Information
Status Register 4
When SRID1=1 and SRID0=1, the contents of the
Status Register 4 are being output in the C-channel
allowing the system to
maintenance channel bits M1 to M6 as specified in
Table 8. The received M-bits may carry the EOC
message (with overhead) as specified in T1.601-
1988. Refer to the “Maintenance Channel“ section
for further details.
Maintenance Channel
The MT8910-1 has provisions for transmitting and
receiving a 4 kbit/s maintenance channel from the
system port to the line port.
channel at the line port is structured into six columns
of which M5 and M6 carry the results of a CRC
calculation (refer to Table 9). All bits except these
CRC bits are treated as a transparent channel to the
MT8910-1. The 12 bit cyclical redundancy check is
computed using the generator polynomial:
The CRC calculation covers all 2B + D-channels
within a superframe as well as the M4 column within
the maintenance channel.
Access to the maintenance channel is granted
through Control Register 3 (Tx M-Channel) and
Status Register 4 (Rx M-Channel) and is structured
on the ST-BUS port as shown in Table 9. The Tx M-
Tx Line Signal
Rx Line Sigmal
SFb pin
RxSFIB bit
Rx Line Signal
Tx Line Signal
SFb pin
RxSFIB bit
LT Mode
NT Mode
(where
x
12
is modulo two summation)
x
ISW
ISW
11
x
3
Figure 10 - Functional Timing for Superframe Signals
monitor
x
2
12x(2B + D)
12x(2B + D)
ISW
ISW
x
The maintenance
7 ST-BUS Frames
1
the received
12x(2B + D)
12x(2B + D)
M
M
SW
SW
bits for all DSL basic frames are written to Control
Register 3 once every 1.5ms within the ST-BUS
frames indicated in Table 9.
update the contents of Control Register 3 within the
allocated window, the M-bits will be substituted by
ones until the information in Control Register 3 is
updated. On the receive path, the Rx M-bits from
each DSL basic frame are available in Status
Register 4 within the ST-BUS frames indicated in
Table 9. The Rx M-bits will be updated every DSL
basic frame (or 1.5 ms).
The M-bits are structured according to the transmit
and receive superframe boundary signals output on
the ST-BUS. The transmit superframe boundary is
defined relative to the input or output SFb signal. (In
LT mode, the transmit superframe boundary can also
be defined in the frame following the TxSFB bit being
set to zero.) The ST-BUS frame in which the SFb
signal is active is defined as transmit frame 0. The
superframe boundary in the receive path is defined
relative to the RxSFIB bit found in Status Register 1.
The ST-BUS frame with RxSFIB=0 is defined as the
receive frame 0. The functional timing diagram for
the phase of the SFb and RxSFIB signals for both
the LT and NT modes is shown in Figure 10.
In applications which do not utilize the maintenance
channel, 2B+D data at the NT and the LT should be
all set to 0 or 1 until activation occurs at the LT.
Since the NT trains up before the LT, the activation at
the LT can be detected at the NT by the reception of
random data. Only then the NT can transmit normal
2B+D data.
M
M
12x(2B + D)
12x(2B + D)
SW
SW
12x(2B + D)
12x(2B + D)
M
M
SW
SW
If the user fails to
MT8910-1
12x(2B + D)
12x(2B + D)
M
M
9-19