MT8910-1 Mitel Networks Corporation, MT8910-1 Datasheet - Page 18

• Manufacturer Part Number: MT8910-1
• Description: CMOS St-bus Family Digital Subscriber Line Interface Circuit
• Manufacturer: Mitel Networks Corporation

MT8910-1
10.24 MHz Clock Interface
The MT8910-1 can operate either with an external
clock or with a built-in oscillator clock using a 10.24
MHz parallel resonance crystal.
external clock, the timing relationship between C4b
and the external clock should be as shown in Figure
15. This is typically used in LT mode. To meet the
specified line performance, the tolerance of the
external clock should be ±5ppm. In NT mode, the
MT8910-1 can use the built-in crystal oscillator
circuit for internal timing, and to meet the specified
line performance, the tolerance of the crystal is
specified to be ±50ppm.
The oscillator in the MT8910-1 uses the Pierce
circuit configuration.
necessary phase shift is obtained by the two
components connected in series; one of them is the
crystal itself, and the other is the RC combination of
the output impedance of the inverter and the
capacitor connected to its output and the ground.
This requires the output impedance of the inverter to
be high for minimizing the power consumption of the
MT8910-1. When OSC1 is used as an input for an
external clock (typically in LT mode), the high output
impedance of the inverter coupled with any stray
capacitance on the OSC2 pin can distort the
waveform and change the duty cycle of the clock
signal fed to the internal blocks of the MT8910-1.
This may result in improper operation. Hence, it is
recommended that an external inverter be connected
in parallel strengthening the internal inverter as
shown in Figure 11.
X=Don’t Care
9-20
Bidirectional
Time Stamp (e.g.: 1 µs)
Signals
Signals
Signals
Output
Input
Z=High Impedance State
CDSTo
TSTout
TSTen
CDSTi
NT/LT
TSTin
MRST
OSC1
OSC2
DSTo
F0od
DSTi
MS0
MS1
C4b
SFb
F0b
In this type of oscillator, the
1
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
2
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
0
0
Initialization
3
X
X
X
X
X
While using the
0
0
0
0
0
0
0
0
0
0
0
0
Table 10. I/O Structure Test Vectors
4
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
1
0
5
X
X
X
X
X
0
0
0
0
0
0
0
0
0
1
1
0
6
0
0
0
0
0
0
0
0
0
X
X
X
X
X
0
1
0
7
0
0
0
0
0
0
0
0
0
X
X
X
X
X
1
0
0
8
1
1
0
1
0
0
0
0
0
X
X
X
X
L
0
0
0
I/O Structure Test
The MT8910-1 has a built-in test structure that
allows verification of all digital I/O structures. The “I/
O Structure Test“ is a static test designed to allow a
parity check on all digital inputs, force all digital
output drivers to any state as well as placing all
digital outputs into a high impedance state. These
three variables can be used to verify the integrity of
the connections between the MT8910-1 and the
printed circuit board.
The I/O structure test has three dedicated pins which
are used to; enable the test structure (TSTen),
provide an output (TSTout) of an XOR chain that is
used to verify all digital input pins, as well as
providing an input signal (TSTin) to all output drivers.
Before enabling the test structure, the default I/O
structure must be cleared to avoid interference with
the test results.
inserting the test vectors as defined in Table 10
below. Once the initialization procedure has been
run, the respective testing mode can be enabled
using the three mode select pins MS0, MS1 and NT/
LT.
The I/O structure test allows the verification of the
connection between the printed circuit board and the
digital input pins to the MT8910-1. After running the
initialization sequence described above, the I/O input
structure test can be enabled by setting TSTen to a
logic high with the mode select pins MS0, MS1 and
NT/LT set to 1, 0, 1 respectively.
digital inputs to be linked into an XOR chain whose
output drives the I/O structure test output (TSTout)
pin
comparison from signals on pins, CDSTi, DSTi,
1
9
X
X
X
X
H
1
1
0
1
0
1
0
0
0
0
0
0
. The TSTout pin will carry the output of the XOR
Input Tests
10 11 12 13 14 15
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
This can be accomplished by
1
1
0
1
0
0
0
0
0
X
X
X
X
L
0
0
0
Preliminary Information
H
1
1
0
1
0
0
0
0
0
X
X
X
X
0
0
1
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
Output Tests
16
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
This forces all
17
1
1
1
0
1
0
0
0
0
1
1
1
1
1
1
1
1
18
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
19
1
1
0
0
0
0
0
0
0
Z
Z
Z
1
Z
Z
Z
Z