MT8926AE Zarlink Semiconductor, MT8926AE Datasheet - Page 11

• Manufacturer Part Number: MT8926AE
• Description: MT8926 - T1 Performance Monitoring Adjunct Circuit (PMAC)
• Manufacturer: Zarlink Semiconductor

SEMICMF.019
Data Sheet
1.7
T1.403 defines SF mode line loopback activate and deactivate codes. These codes are either a framed or un-
framed repeating bit sequence of 00001 for activation or 001 for deactivation. The standard goes on to say that
these codes will persist for five seconds or more before the loopback action is taken.
The MT8926 will generate line loopback activate and de-activate codes. These functions are controlled by the
Loopback Control Word of CSTi1 channel 15 (see Table 4 on page 9). The connections illustrated in Figure 6 on
page 8 must be implemented for this feature to function.
The MT8926 will also detect both framed and un-framed line loopback activate and de-activate codes even in the
presence of a BER of 3 errors in 1000 bits. See the PMAC Miscellaneous Status Word, Table 5 on page 10, CSTo
channel 7 bit 3 Line Loopback Enable Detect (LLED) and bit 4 Line Loopback Disable Detect (LLDD). The line
loopback of T1.403 is equivalent to the remote loopback function of the MT8976/77 (see MT8976/77 data sheet,
Master Control Word 2). Therefore, the user will monitor the LLED and LLDD bits to ensure that they persist for a
minimum of five seconds. Then the line loopback can be either activated or de-activated using the MT8976/77
Remote Loopback function.
1.8
The MT8926 has its own frame synchronization mechanism, which uses the received signal (RxA and RxB) and
E8Ki to achieve SF and ESF frame and superframe alignment. Further, the PMAC monitors the SYN bit of the
MT8976/77 (CSTo channel 15 bit 0) and will not declare synchronization until it is clear. When SYN is low and the
MT8926 framer is properly aligned for two superframes, the PMAC will declare synchronization by making the
Frame Error Count Validation bit (FECV) high. If this criteria is not met, FECV will be low.
The PMAC will use the received F
or FPS bits are used to determine the out-of-synchronization state (see Table 5 on page 10).
Bit
2
1
0
Line Loopback Codes
PMAC Synchronization
Table 5 - PMAC Miscellaneous Status Word (CSTo Channel 7) (continued)
BOMV
Name
FECV
TMR
Framing Error Count Validation. This bit is set when the MT8926 has synchronized
to a framed T1 signal. The framing error count is frozen if this bit is not set.
Synchronization (FECV=1) is reported when the MT8926 detects two consecutive
superframes with correct framing bits, and bit 0 in CSTi0 channel 15 (SYN) is zero.
When receiving an SF signal, both F
the PMAC Control word is set. In this case the sixth F
checking for framing bits. If bit FSel is reset, then only F
Loss of synchronization (FECV=0) is reported when either two out of four errors
have been detected in the received framing bit position (SF F
bits) or if bit 0 in CSTi0 channel 15 (SYN) is set indicating the MT8976/77 has lost
synchronization.
Two Second Timer. This bit changes state once per second.
Bit-Oriented Message Validation. This bit will be set when a valid bit-oriented
message is present in the receive BOM register (Table 12 on page 15, CSTo,
channel 27). It is reset when a valid message is not being received. A valid bit-
oriented message has the form 111111110XXXXXX0, where XXXXXX contains
the message information.
T
and F
S
bits, F
T
bits only or FPS bits to acquire synchronization. The receive F
Description
S
and F
T
bits are examined if bit 3 (FSel) in
S
bit is not examined when
T
bits are examined.
T
bits or ESF FPS
MT8926
11
T