MT8926AE Zarlink Semiconductor, MT8926AE Datasheet - Page 20

• Manufacturer Part Number: MT8926AE
• Description: MT8926 - T1 Performance Monitoring Adjunct Circuit (PMAC)
• Manufacturer: Zarlink Semiconductor

MT8926
20
‡ G2 interrupts are cleared when SEI, FSI, CSI and BSI = 0.
Note: AND denotes a logical and.
Signal
CSI
SEI
FSI
BSI
‡
SEI bit low to high AND other G2
interrupts quiescent AND IRQ
high impedance.
FSI bit low to high AND other G2
interrupts quiescent AND IRQ
high impedance.
CSI bit low to high AND other G2
interrupts quiescent AND IRQ
high impedance.
BSI bit low to high AND other G2
interrupts quiescent AND IRQ
high impedance.
To Trigger interrupt (IRQ low)
Table 17 - Group Two (G2) Interrupt Activation and Clearing
The INTA bit of the PMAC Control Word (CSTi1 channel 11 bit
1) should be made low to clear the interrupt mechanism (IRQ
high impedance). All G2 interrupts must be clear and INTA
must be high before a further interrupt can be generated from
G2.
The SEI bit will remain clear as long as the INTA bit is low. SEI
can also be cleared (low) by toggling SER (CSTi1 channel 11
bit 7) from high to low.
FSI is cleared (low) by toggling FER (CSTi1 channel 11 bit 6)
from high to low.
CSI is cleared (low) by toggling CRCR (CSTi1 channel 11 bit 5)
from high to low. Valid for ESF only.
BSI is cleared (low) by toggling BPVR (CSTi1 channel 11 bit 4)
from high to low.
To Clear and Arm interrupt
(
IRQ high impedance)
Data Sheet
SEMICMF.019