MPC9608 Motorola Inc, MPC9608 Datasheet - Page 3

• Manufacturer Part Number: MPC9608
• Description: 1:10 LVCMOS Zero Delay Clock Buffer
• Manufacturer: Motorola Inc

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TABLE 1. PIN CONFIGURATION
CCLK
FB_IN
F_RANGE[0:1]
BSEL
PLL_EN
OE
CLK_STOP
QA0-4, QB0-4
QFB
GND
VCCA
VCC
TABLE 2. FUNCTION TABLE
TABLE 3. Clock Frequency Configuration for QFB connected to FB_IN
TIMING SOLUTIONS
F_RANGE[0:1]
F_RANGE[0]
CLK_STOP
Control
PLL_EN
BSEL
Pin
OE
0
0
0
0
1
1
1
1
F_RANGE[1]
Input
Input
Input
Input
Input
Input
Input
Output
Output
Supply
Supply
Supply
Default
00
0
0
0
0
I/O
0
0
1
1
0
0
1
1
PLL frequency range. Refer to Table 3 “Clock frequency configuration for QFB connected to FB_IN”
f
Outputs enabled
Outputs enabled (active)
Normal operation mode with PLL enabled.
QB0-4
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
VCC
VCC
Type
= f
Freescale Semiconductor, Inc.
BSEL
QA0-4
0
1
0
1
0
1
0
1
For More Information On This Product,
PLL reference clock signal
PLL feedback signal input, connect to a QFB output
PLL frequency range select
Frequency divider select for bank B outputs
PLL enable/disable
Output enable/disable (high-impedance tristate)
Synchronous clock enable/stop
Clock outputs
PLL feedback signal output. Connect to FB_IN
Negative power supply
PLL positive power supply (analog power supply). The MPC9608 requires an external RC filter for
the analog power supply pin V
Positive power supply for I/O and core
0
100.0 – 200.0
Go to: www.freescale.com
f
range [MHz]
50.0 – 100.0
REF
25.0 – 50.0
12.5 – 25.0
(CCLK)
Ratio
f
f
f
f
REF
REF
REF
REF
CCA.
f
Outputs synchronously stopped in logic low state
Outputs disabled (high-impedance state), independent on
CLK_STOP. Applying
PLL feedback output QFB is not affected by
Test mode with PLL disabled. CCLK is substituted for the internal
VCO output. MPC9608 is fully static and no minimum frequency limit
applies. All PLL related AC characteristics are not applicable.
Applying
QB0-4
QA0-QA4
Refer to the Applications Information section for details.
= f
100.0 – 200.0
f
50.0 – 100.0
QA0-4
OE
QA0-4
25.0 – 50.0
12.5 – 25
= 1 and
Function
[MHz]
2
PLL_EN
OE
= 1 and
f
f
f
f
REF
REF
REF
REF
Ratio
= 1 resets the device.
f
f
f
f
REF
REF
REF
REF
1
PLL_EN
2
2
2
2
QB0-B4
= 1 resets the device. The
100.0 – 200.0
f
50.0 – 100.0
QB0-4
50.0 – 25.0
25.0 – 50.0
25.0 – 50.0
12.5 – 25.0
12.5 – 25.0
6.25 – 12.5
OE
.
[MHz]
MPC9608
QFB
f
f
f
f
f
f
f
f
REF
REF
REF
REF
REF
REF
REF
REF
3