MPC9608 Motorola Inc, MPC9608 Datasheet - Page 7

• Manufacturer Part Number: MPC9608
• Description: 1:10 LVCMOS Zero Delay Clock Buffer
• Manufacturer: Motorola Inc

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is specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 8.
and can be used to fine-tune the effective delay through each
device. In the following example calculation a I/O jitter confi-
dence factor of 99.7% ( 3 ) is assumed, resulting in a worst
case timing uncertainty from input to any output of -295 ps to
295 ps
Driving Transmission Lines
speed signals in a terminated transmission line environment. To
provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of less than 20
ther parallel or series terminated transmission lines. For more
information on transmission lines the reader is referred to Mo-
torola application note AN1091. In most high performance clock
networks point-to-point distribution of signals is the method of
choice. In a point-to-point scheme either series terminated or
parallel terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a 50
resistance to V
thus only a single terminated line can be driven by each output
of the MPC9608 clock driver. For the series terminated case
however there is no DC current draw, thus the outputs can drive
multiple series terminated lines. Figure 5 “Single versus Dual
Transmission Lines” illustrates an output driving a single series
terminated line versus two series terminated lines in parallel.
When taken to its extreme, the fanout of the MPC9608 clock
driver is effectively doubled due to its capability to drive multiple
lines.
1. Skew data are designed targets and pending device specifcations.
TABLE 8. Confidence Facter CF
TIMING SOLUTIONS
CF
Due to the statistical nature of I/O jitter, an RMS value (1 )
The feedback trace delay is determined by the board layout
t
t
The MPC9608 clock driver was designed to drive high
This technique draws a fairly high level of DC current and
SK(PP)
SK(PP)
1
2
3
4
5
6
1
relative to CCLK:
=
=
Probability of clock edge within the distribution
CC
[-100 ps...100 ps] + [-150 ps...150 ps] +
[(15 ps -3)...(15 ps 3)] + t
[-295 ps...295 ps] + t
2.
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
Freescale Semiconductor, Inc.
For More Information On This Product,
PD, LINE(FB)
the drivers can drive ei-
PD, LINE(FB)
Go to: www.freescale.com
Termination Waveforms” show the simulation results of an out-
put driving a single line versus two lines. In both cases the drive
capability of the MPC9608 output buffer is more than sufficient
to drive 50
delay measurements in the simulations a delta of only 43 ps ex-
ists between the two differently loaded outputs. This suggests
that the dual line driving need not be used exclusively to main-
tain the tight output-to-output skew of the MPC9608. The output
waveform in Figure 6 “Single versus Dual Line Termination
Waveforms” shows a step in the waveform. This step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 36
impedance does not match the parallel combination of the line
impedances. The voltage wave launched down the two lines will
equal:
near unity reflection coefficient. It will then increment towards
the quiescent 3.0 V in steps separated by one round trip delay
(in this case 4.0 ns).
IN
IN
At the load end the voltage will double to 2.6 V due to the
The waveform plots in Figure 6 “Single versus Dual Line
Figure 5. Single versus Dual Transmission Lines
MPC9608
MPC9608
OUTPUT
OUTPUT
BUFFER
BUFFER
14
14
transmission lines on the incident edge. From the
V
Z
R
R
V
L
0
L
S
0
= V
= 50
= 36
= 14
= 3.0 ( 25
= 1.31 V
S
R
R
R
( Z
S
S
S
|| 36
0
|| 50
= 36
= 36
= 36
(R
(18 + 17 + 25))
series resistor plus the output
S
+ R
Z
Z
Z
O
O
O
0
= 50
= 50
= 50
+ Z
0
))
OutA
OutB0
OutB1
MPC9608
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