ADC0806 National Semiconductor, ADC0806 Datasheet - Page 12

• Manufacturer Part Number: ADC0806
• Description: 500 ns A/D Converter with S/H Function and Input Multiplexer
• Manufacturer: National Semiconductor

www.national.com
Specification Definitions
APERTURE (SAMPLING) DELAY is that time required after
the fall of the clock input for the sampling switch to open. The
Sample/Hold circuit effectively stops capturing the input sig-
nal and goes into the “hold” mode t
low.
APERTURE JITTER is the variation in aperture delay from
sample to sample. Aperture jitter shows up as noise at the
output.
CLOCK DUTY CYCLE is the ratio of the time that the clock
wavesform is at a logic high to the total time of one clock
period.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
Measured at 60 MSPS with a ramp input.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD –
1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
FULL-POWER BANDWIDTH is the frequency at which the
reconstructed output fundamental drops 3 dB below its low
frequency value for a full scale input.
FULL-SCALE ERROR is a measure of how far the last code
transition is from the ideal 1
as:
where V
maximum (full scale) code occurs.
INTEGRAL NON-LINEARITY (INL) is a measure of the
deviation of each individual code from a line drawn from zero
scale (
full scale (
tion of any given code from this straight line is measured
from the center of that code value. The end point test method
is used. Measured at 60 MSPS with a ramp input.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of the interaction
between two sinusoidal frequencies that are applied to the
ADC input at the same time. IMD is the ratio of the power in
the second and third order intermodulation products to the
total power in the original frequencies.
MISSING CODES are those output codes that are skipped
and will never appear at the ADC outputs. These codes
cannot be reached with any input value.
POWER SUPPLY REJECTION RATIO (PSRR) is a mea-
sure of how well the ADC rejects a change in the power
supply voltage. For the ADC08060, PSRR1 is the ratio of the
change in dc power supply voltage to the resulting change in
Full-Scale Error, expressed in dB. PSRR2 is a measure of
1
⁄
2
max
LSB below the first code transition) through positive
1
⁄
2
LSB above the last code transition). The devia-
is the voltage at which the transition to the
V
max
+ 1.5 LSB – V
1
⁄
2
LSB below V
AD
RT
after the clock goes
RT
and is defined
12
how well an a.c. signal riding upon the power supply is
rejected and is here defined as:
where SNR0 is the SNR measured with no noise or signal on
the supply lines and SNR1 is the SNR measured with a 200
kHz, 200 mV
OUTPUT DELAY is the time delay after the rising edge of
the input clock before the data changes at the output pins.
OUTPUT HOLD TIME is the length of time that the output
data is valid after the rise of the input clock.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is pre-
sented to the output driver stage. New data is available at
every clock cycle, but the data lags the conversion by the
Pipeline Delay plus the Output Delay.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal frequency at the
output to the rms value of the sum of all other spectral
components below one-half the sampling frequency, not in-
cluding harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or
SINAD) is the ratio, expressed in dB, of the rms value of the
input signal frequency at the output to the rms value of all of
the other spectral components below half the clock fre-
quency, including harmonics but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the rms values of the input
signal frequency at the output and the peak spurious signal,
where a spurious signal is any signal present in the output
spectrum that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dB, of the total of the first nine harmonic levels at
the output to the level of the fundatmental at the output. THD
is calculated as
where f
quency and f
ics in the output spectrum.
ZERO SCALE OFFSET ERROR is the error in the input
voltage required to cause the first code transition. It is de-
fined as
where V
1
ZT
is the RMS power of the fundamental (input) fre-
is the first code transition input voltage.
2
P-P
through f
signal riding upon the supply lines.
V
OFF
10
is the power in the first 9 harmon-
= V
ZT
− V
RB