ADC08L060CIMT National Semiconductor, ADC08L060CIMT Datasheet - Page 13

• Manufacturer Part Number: ADC08L060CIMT
• Description: 8-Bit/ 10 MSPS to 60 MSPS/ 0.65 mW/MSPS A/D Converter with Internal Sample-and-Hold
• Manufacturer: National Semiconductor

Functional Description
The ADC08L060 uses a unique architecture that achieves
over 7 effective bits at input frequencies up to and beyond
Nyquist.
The analog input signal that is within the voltage range set by
V
V
voltages above V
all ones.
Incorporating
ADC08L060 exhibits a power consumption that is propor-
tional to frequency, limiting power consumption to what is
needed at the clock rate that is used. This and its excellent
performance over a wide range of clock frequencies makes
it an ideal choice as a single ADC for many 8-bit needs.
Data is acquired at the rising edge of the clock and the digital
equivalent of that data is available at the digital outputs 5
clock cycles plus t
long as an adequate clock signal is present at pin 24. The
The reference bias circuit of Figure 2 is very simple and the
performance is adequate for many applications. However,
circuit tolerances will lead to a wide reference voltage range.
Better reference stability can be achieved by driving the
reference pins with low impedance sources.
The circuit of Figure 3 will allow a more accurate setting of
the reference voltages. The lower amplifier must have bipo-
lar supplies as its output voltage must go negative to force
V
course, the divider resistors at the amplifier input could be
changed to suit your reference voltage needs, or the divider
RT
RB
FIGURE 2. Simple, low component count reference biasing. Because of the ladder and external resistor tolerances,
RB
and V
will cause the output word to consist of all zeroes. Input
to any voltage below the V
RB
is digitized to eight bits. Input voltages below
a
RT
OD
switched
will cause the output word to consist of
later. The ADC08L060 will convert as
the reference voltage can vary too much for some applications.
BE
capacitor
of the PNP transistor. Of
bandgap,
the
13
device is in the active state when the Power Down pin (PD)
is low. When the PD pin is high, the device is in the power
down mode, where the output pins hold the last conversion
before the PD pin went high and the device consumes just
1 mW.
Applications Information
1.0 REFERENCE INPUTS
The reference inputs V
the reference ladder, respectively. Input signals between
these two voltages will be digitized to 8 bits. External volt-
ages applied to the reference input pins should be within the
range specified in the Operating Ratings table (0.5V to (V
0.3V) for V
used to drive the reference pins should be able to source
sufficient current into the V
from the V
can be replaced with potentiometers for precise settings.
The bottom of the ladder (V
ground if the minimum input signal excursion is 0V. Be sure
that the driving source can source sufficient current into the
V
these pins stable.
The LMC662 amplifier shown was chosen for its low offset
voltage and low cost. V
more positive than V
RT
pin and sink enough current from the V
RB
RT
pin to keep these voltages stable.
and 0V to (V
RB
RT
to minimize noise.
RT
and V
RT
RT
should always be at least 0.5V
RB
pin and sink sufficient current
20041732
− 0.5V) for V
) may simply be returned to
RB
are the top and bottom of
RB
RB
). Any device
pin to keep
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A
−