TS68020 ATMEL Corporation, TS68020 Datasheet - Page 13

• Manufacturer Part Number: TS68020
• Description: Hcmos 32-bit Virtual Memory Mpu, 16/20/25 MHZ
• Manufacturer: ATMEL Corporation

Table 6. Dynamic Electrical Characteristics (Continued)
Notes:
2115A–HIREL–07/02
Symbol
f
t
t
t
t
t
RADC
HRPW
BNHN
GANBD
GNBD
1. This number can be reduced to 5 nanoseconds if the strobes have equal loads.
2. If the asynchronous setup time (= 47) requirements are satisfied, the DSACKx low to data setup time (= 31) and DSACKx
3. This parameter specifies the maximum allowable skew between DSACK0 to DSACK1 asserted or DSACK1 to DSACK0
4. In the absence of DSACKx, BERR is an asynchronous input using the asynchronous input setup time (= 47).
5. DBEN may stay asserted on consecutive write cycles.
6. Actual value depends on the clock input waveform.
7. This pattern indicates the minimum high time for ECS and OCS in the event of an internal cache hit followed immediately by
8. This specification guarantees operations with the 68881 co-processor, and defines a minimum time for DS negated to AS
9. This pattern allows the systems designer to guarantee data hold times on the output side of data buffers that have output
10. Guarantees that an alternate bus master has stopped driving the bus when the 68020 regains control of the bus after an
11. Cannot be tested. Provided for system design purposes only.
12. T
13. All outputs unload except for load capacitance. Clock = fmax,
low to BERR low setup time (= 48) can be ignored. The data must only satisfy the data in to clock low setup time (= 27) for
the following clock cycle, BERR must only satisfy the late BERR low to clock setup time (= 27) for the following clock cycle.
asserted pattern = 47 must be met by DSACK0 and DSACK1.
a cache miss or operand cycle.
asserted (= 13A). Without this parameter, incorrect interpretation of = 9A and = 15 would indicate that the 68020 does not
meet 68881 requirements.
enable signals generated with DBEN.
arbitration sequence.
parameters are tested “instant on” 100 m sec. after power is applied.
LOW: HALT, RESET
HIGH: DSACK0, DSACK1, CDIS, IPL0-IPL2, DBEN, AVEC, BERR.
Parameter
Frequency of Operation
R/W Asserted to Data Bus Impedance
Change
RESET Pulse Width (Reset Instruction)
BERR Negated to HALT Negated
(Rerun)
BGACK Negated to Bus Driven
BG Negated to Bus Driven
case
= -55
°
C and +130
°
C in a Power off condition under Thermal soak for 4 minutes or until thermal equilibrium. Electrical
Number
Interval
55
56
57
58
59
Min
512
8.0
30
0
1
1
68020-16
16.67
Max
12.5
Min
512
25
68020-20
0
1
1
Max
20.0
12.5
Min
512
20
0
1
1
68020-25
Max
25
TS68020
MHz
Clks
Clks
Clks
Unit
ns
Notes
(10)(11)
(10)(11)
(11)
(11)
(11)
13