TS68020 ATMEL Corporation, TS68020 Datasheet - Page 39

• Manufacturer Part Number: TS68020
• Description: Hcmos 32-bit Virtual Memory Mpu, 16/20/25 MHZ
• Manufacturer: ATMEL Corporation

Figure 22. TS68020 On-chip Cache Organization
2115A–HIREL–07/02
Second, and probably the most important benefit of the cache, is that it allows instruc-
tion stream fetches and operand accesses to proceed in parallel. For example, if the
TS68020 requires both an instruction stream access and an operand access, and the
instruction is resident in the cache, the operand access will proceed unimpeded rather
than being queued behind the instruction fetch. Similarly, the TS68020 is fully capable of
executing several internal instructions (instructions that do not require the bus) while
completing an operand access for another instruction.
The TS68020 instruction cache is a 256-byte direct mapped cache organized as 64 long
word entries. Each cache entry consists of a tag field made up of the upper 24 address
bits, the FC2 (user/supervisor) value, one valid bit, and 32-bit of instruction data (Figure
22).
The TS68020 employs a 32-bit data bus and fetches instructions on long word address
boundaries. Hence, each 32-bit instruction fetch brings in two 16-bit instruction words
which are then written into the on-chip cache. When the cache is enabled, the subse-
quent prefetch will find the next 16-bit instruction word is already present in the cache
and the related bus cycle is saved. If the cache were not enabled, the subsequent
prefetch will find the bus controller still holds the full 32-bit and can satisfy the prefetch
and again save the related bus cycle. So, even when the on-chip instruction cache is not
enabled, the bus controller provides an instruction “cache hit” rate up to 50%.
TS68020
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