DS3150 Maxim Integrated Products, DS3150 Datasheet

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DS3150

Manufacturer Part Number
DS3150
Description
3.3V T3 / E3 / STS-1 Line Interface Unit
Manufacturer
Maxim Integrated Products
Datasheet

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Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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GENERAL DESCRIPTION
The DS3150 performs all the functions necessary for
interfacing at the physical layer to DS3, E3, and
STS-1 lines. The receiver performs clock and data
recovery, B3ZS/HDB3 decoding, and loss-of-signal
monitoring. The transmitter encodes outgoing data
and drives standards-compliant waveforms onto 75Ω
coaxial cable. The jitter attenuator can be mapped
into the receive path or the transmit path.
APPLICATIONS
SONET/SDH and PDH Multiplexers
Digital Cross-Connects
Access Concentrators
ATM and Frame Relay Equipment
Routers
PBXs
DSLAMs
CSUs/DSUs
ORDERING INFORMATION
FUNCTIONAL DIAGRAM
DS3150QN
DS3150Q
DS3150TN
DS3150T
LINE OUT
DS3, E3,
DS3, E3,
LINE IN
PART
STS-1
STS-1
RX+
RX-
TX+
TX-
-40°C to +85°C
-40°C to +85°C
TEMP RANGE
0°C to +70°C
0°C to +70°C
DS3150
LIU
RNEG
RPOS
TNEG
TPOS
RCLK
TCLK
PIN-PACKAGE
28 PLCC
28 PLCC
48 TQFP
48 TQFP
RECEIVE
CLOCK
AND DATA
TRANSMIT
CLOCK
AND DATA
1 of 27
FEATURES
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Pin Configurations appear at end of data sheet.
Integrated Transmitter, Receiver, and Jitter
Attenuator for DS3, E3, and STS-1
Performs Receive Clock/Data Recovery and
Transmit Waveshaping
Jitter Attenuator Can Be Placed in the Receive
Path or the Transmit Path
AGC/Equalizer Block Handles from 0dB to
15dB of Cable Loss
Interfaces to 75W Coaxial Cable at Lengths Up to
380m (DS3), 440m (E3), or 360m (STS-1)
Interfaces Directly to a DSX Monitor Signal
(20dB Flat Loss) Using Built-In Preamp
Built-In B3ZS and HDB3 Encoder/Decoder
Bipolar and NRZ Interfaces
Local and Remote Loopbacks
On-Board 2
Sequence (PRBS) Generator and Detector
Line Build-Out (LBO) Control
Transmit Line-Driver Monitor Checks for a
Faulty Transmitter or a Shorted Output
Complete DS3 AIS Generator (ANSI T1.107)
Unframed All-Ones Generator (E3 AIS)
Clock Inversion for Glueless Interfacing
Tri-State Line Driver for Low-Power Mode and
Protection Switching Applications
Loss-of-Signal (LOS) Detector (ANSI T1.231
and ITU G.775)
Requires Minimal External Components
Drop-In Replacement for TDK 78P2241/B and
78P7200L (Refer to Application Note 362)
Pin Compatible with TDK 78P7200
3.3V Operation (5V Tolerant I/O), 110mA (max)
Industrial Temperature Range: -40°C to +85°C
Small Packaging: 28-Pin PLCC and 48-Pin
TQFP
15
3.3V DS3/E3/STS-1
Line Interface Unit
- 1 and 2
DEMO KIT AVAILABLE
23
- 1 Pseudorandom Bit
DS3150
010703

Related parts for DS3150

DS3150 Summary of contents

Page 1

... GENERAL DESCRIPTION The DS3150 performs all the functions necessary for interfacing at the physical layer to DS3, E3, and STS-1 lines. The receiver performs clock and data recovery, B3ZS/HDB3 decoding, and loss-of-signal monitoring. The transmitter encodes outgoing data and drives standards-compliant waveforms onto 75Ω ...

Page 2

DETAILED DESCRIPTION.................................................................................................4 1.1 R .................................................................................................................................... 7 ECEIVER 1.2 T .............................................................................................................................10 RANSMITTER 1.3 D ..............................................................................................................................15 IAGNOSTICS 1 ...................................................................................................................16 ITTER TTENUATOR 2. PIN DESCRIPTIONS ........................................................................................................17 3. ELECTRICAL CHARACTERISTICS ................................................................................21 4. PIN CONFIGURATIONS ..................................................................................................25 5. PACKAGE INFORMATION..............................................................................................26 TABLE OF CONTENTS ...

Page 3

Figure 1-1. Block Diagram ...........................................................................................................4 Figure 1-2. External Connections.................................................................................................6 Figure 1-3. Receiver Jitter Tolerance...........................................................................................9 Figure 1-4. E3 Waveform Template ...........................................................................................13 Figure 1-5. DS3 AIS Structure ...................................................................................................14 Figure 1-6. PRBS Output with Normal RCLK Operation ............................................................15 Figure 1-7. PRBS Output with ...

Page 4

... DETAILED DESCRIPTION The DS3150 performs all the functions necessary for interfacing at the physical layer to DS3, E3, and STS-1 lines. The device has independent receive and transmit paths and a built-in jitter attenuator (Figure 1-1). The receiver performs clock and data recovery from a B3ZS- or HDB3-coded alternate mark inversion (AMI) signal and monitors for loss-of-signal ...

Page 5

Table 1-A. Applicable Telecommunications Standards SPECIFICATION T1.102-1993 Digital Hierarchy—Electrical Interfaces T1.107-1995 Digital Hierarchy—Formats Specification Digital Hierarchy—Layer 1 In-Service Digital Transmission Performance T1.231-1997 Monitoring T1.404-1994 Network-to-Customer Installation—DS3 Metallic Interface Specification G.703 Physical/Electrical Characteristics of Hierarchical Digital Interfaces, 1991 Digital Multiplex Equipment ...

Page 6

... TD07- Halo Electronics 0206NE Note: Table subject to change. Industrial temperature range and dual transformers also available. Contact the manufacturers for details. VDD TX+ DD VDD 330W (1%) 0.05µF VDD TX- DS3150 VSS RX+ VSS 330W (1%) 0.05µF VSS RX- PIN- TEMP RANGE PACKAGE/ SCHEMATIC 6-SMT 0°C to +70°C ...

Page 7

Receiver Interfacing to the Line. The receiver can be transformer-coupled or capacitor-coupled to the line. Typically, the receiver interfaces to the incoming coaxial cable (75W) through a 1:2 step-up transformer. Figure 1-2 shows the arrangement of the transformer and ...

Page 8

For E3 LOS Assertion: 1) The ALOS circuitry detects that the incoming signal is less than or equal to a signal level approximately 24dB below nominal and mutes the data coming out of the clock and data recovery block. (24dB ...

Page 9

... RMON pin setting. Note 2: The low-frequency plateau seen in most of the jitter tolerance curves is not the actual performance of the DS3150 but rather the limit of the measuring equipment (64UIp-p). Actual jitter tolerance in these low-frequency ranges is greater than or equal to 64UIp-p ...

Page 10

Transmitter Transmit Clock. The clock applied at the TCLK input is used to clock in data on the TPOS/TNRZ and TNEG pins. If the jitter attenuator is not enabled in the transmit path, the signal on TCLK is the ...

Page 11

Transmit Driver Monitor. If the transmit driver monitor detects a faulty transmitter, it activates the DM output pin. When the transmitter is tri-stated (TTS = 0), the transmit driver monitor is also disabled. The transmitter is declared to be faulty ...

Page 12

Table 1-E. STS-1 Waveform Template TIME (UNIT INTERVALS) -0.85 £ T £ -0.68 -0.68 £ T £ 0.26 0.26 £ T £ 1.4 -0.85 £ T £ -0.36 -0.36 £ T £ 0.36 0.36 £ T £ 1.4 Table 1-F. ...

Page 13

Figure 1-4. E3 Waveform Template 1.2 1.1 1.0 0.9 0.8 0.7 Output 0.6 Level (V) 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 Table 1-G. E3 Waveform Test Parameters and Limits PARAMETER Rate Line Code Transmission Medium Test Measurement Point ...

Page 14

Figure 1-5. DS3 AIS Structure M1 Subframe Info F1 Info C1 (1) Bits (1) Bits (0) M2 Subframe Info F1 Info C1 (1) Bits (1) Bits (0) M3 Subframe Info F1 ...

Page 15

... Diagnostics PRBS Generator and Detector. The DS3150 contains on-board pseudorandom bit sequence (PRBS) generator and detector circuitry for physical layer testing. The device generates and detects unframed (DS3 or STS- generator is enabled through the TDS0 and TDS1 inputs is always enabled and reports its status on the PRBS output pin. When the PRBS detector is out of synchronization, the PRBS pin is forced high ...

Page 16

... Jitter Attenuator The DS3150 contains an on-board jitter attenuator (JA) that can be placed in the receive path or in the transmit path or disabled. This selection is made using the RMON and TTS input pins. See selection details. Figure 1-8 shows the minimum jitter attenuation for the device when the JA is enabled. ...

Page 17

... DM O faulty transmitter driven low. Requires an external pullup to VDD. Not bonded out in the PLCC package. Enhanced Feature Enable. EFE enables the enhanced DS3150 features (PRBS generation/detection and the transmission of patterns, including all ones, DS3 AIS, and I3 the 1010… pattern). ...

Page 18

NAME TYPE error detected. See is tri-stated. The PRBS pin is only available in the TQFP package type. Receive Clock. The recovered clock is output on the RCLK pin. The recovered data is updated at the RPOS/RNRZ and RNEG/RLCV outputs ...

Page 19

NAME TYPE Transmit Negative Data. When the B3ZS/HDB3 encoder is disabled (ZCSE = 1), TNEG should be driven high to transmit a negative AMI pulse. When the B3ZS/HDB3 I3 TNEG encoder is enabled (ZCSE = 0), the NRZ data stream ...

Page 20

Table 2-B. Transmit Data Selection TDS1 TDS0 TESS Float Transmit unframed 101010… pattern Float Transmit 2 Note: When EFE is ...

Page 21

ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to V Supply Voltage Range (V ) with Respect Operating Temperature Range Storage Temperature Range Soldering Temperature Range Stresses beyond those listed under “Absolute ...

Page 22

FRAMER INTERFACE TIMING (V = 3.3V ±5 -40°C to +85°C PARAMETER RCLK/TCLK Clock Period RCLK Clock High/Low Time TCLK Clock High/Low Time TPOS/TNRZ, TNEG to TCLK Setup Time TPOS/TNRZ, TNEG Hold Time RCLK to RPOS/RNRZ Valid, ...

Page 23

... Note 9: An interfering signal ( PRBS for DS3/STS- added to the wanted signal. The combined signal is passed through 0 to 900 feet of coaxial cable and presented to the DS3150 receiver. This spec indicates the lowest signal-to-noise ratio that results in a bit error ratio < 10 Note 10: Not tested during production test ...

Page 24

TRANSMITTER OUTPUT CHARACTERISTICS—DS3 AND STS-1 MODES (V = 3.3V ±5 -40°C to +85°C PARAMETER DS3 Output Pulse Amplitude, LBO = 0 (Note 13) DS3 Output Pulse Amplitude, LBO = 1 (Note 13) STS-1 Output Pulse Amplitude, ...

Page 25

... DM TX+ ICE TX- VSS VSS 6 VDD 7 DS3150 VSS 8 TX+ 9 ICE 10 TX PLCC DS3150 TQFP RPOS/RNRZ 24 RNEG/RLCV 23 RCLK 22 VSS 21 RMON 20 ZCSE 19 MCLK 18 36 VSS 35 RPOS/RNRZ 34 RNEG/RLCV 33 RCLK 32 VSS 31 VSS 30 ...

Page 26

PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo.) 28-Pin PLCC Dimensions: millimeters Thermal Information +68°C/W JA DIM MIN A 0.165 ...

Page 27

TQFP Dimensions: millimeters Thermal Information +46°C/W JA DIM MIN A — A1 0.05 A2 0.95 D 8.80 D1 7.00 BSC E 8.80 E1 7.00 BSC L 0.45 E 0.50 BSC B 0. ...

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