DS3150 Maxim Integrated Products, DS3150 Datasheet - Page 18

• Manufacturer Part Number: DS3150
• Description: 3.3V T3 / E3 / STS-1 Line Interface Unit
• Manufacturer: Maxim Integrated Products

NAME
RMON
RNEG/
OFSEL
RPOS/
RCLK
RLCV
RNRZ
TDS1/
TCLK
TDS0
TESS
RX+,
RX-
(Note 2)
(Note 2)
(Note 2)
(Note 2)
TYPE
I3
I3
I3
I3
O
O
O
I
I
error detected. See
is tri-stated. The PRBS pin is only available in the TQFP package type.
Receive Clock. The recovered clock is output on the RCLK pin. The recovered data is
updated at the RPOS/RNRZ and RNEG/RLCV outputs on either the falling edge of
RCLK (ICE = 0 or 1) or the rising edge of RCLK (ICE = FLOAT). During loss of
signal (LOS = 0), the RCLK output signal is derived from the device’s master clock.
Receive Monitor Mode. RMON determines whether or not the receiver’s preamp is
enabled to provide flat to the incoming signal before it is processed by the equalizer.
This feature should be enabled when the device is being used to monitor signals that
have been resistively attenuated by a monitor jack.
This input also controls the jitter attenuator
0 = disable the monitor preamp, disable the jitter attenuator in the receive path
1 = enable the monitor preamp, disable the jitter attenuator in the receive path
Float = disable the monitor preamp, enable the jitter attenuator in the receive path
Receive Negative Data or Receive Line Code Violation. When the B3ZS/HBD3
decoder is disabled (ZCSE = 1), RNEG pulses high to indicate reception of a negative
AMI pulse. When the B3ZS/HDB3 decoder is enabled (ZCSE = 0), the NRZ data
stream is output on RNRZ while RLCV is pulsed high for one RCLK period whenever
the decoder sees a line coding violation. RNEG/RLCV is updated either on the rising
edge of RCLK (ICE = Float) or the falling edge of RCLK (ICE = 0 or 1).
Receive Positive Data or Receive NRZ Data. When the B3ZS/HBD3 decoder is
disabled (ZCSE = 1), RPOS pulses high to indicate reception of a positive AMI pulse.
When the B3ZS/HDB3 decoder is enabled (ZCSE = 0), the NRZ data stream is output
on RNRZ while RLCV is pulsed high whenever the decoder sees a line coding
violation. RPOS/RNRZ is updated either on the rising edge of RCLK (ICE = Float) or
the falling edge of RCLK (ICE = 0 or 1).
Receive Analog Inputs. These differential AMI inputs are coupled to the inbound 75W
coaxial cable through a 1:2 step-up transformer
Transmit Clock. A DS3 (44.736MHz), E3 (34.368MHz), or STS-1 (51.840MHz) clock
should be applied to the TCLK pin. Data to be transmitted is clocked into the device at
TPOS/TNRZ and TNEG either on the rising edge of TCLK (ICE = 0) or the falling
edge of TCLK (ICE = 1 or FLOAT). The duty cycle on TCLK is not restricted as long
the high and low times listed in Section
Transmit Data Select Bit 0. If EFE = 1, TDS0, TDS1 and TESS select the source of the
transmit data
Transmit Data Select Bit 1/Oscillator Frequency Select. If EFE = 1, TDS1, TDS0 and
TESS select the source of the transmit data
MCLK is wired low, TDS1 is internally pulled low, and a resistor connected between
this pin (OFSEL) and ground determines the frequency of an internal oscillator. The
following resistor values should be used for specific applications:
E3: 6.81kW, ±2%
DS3: 5.23kW, ±2%
STS-1: 4.53kW, ±2%
When switching among DS3, E3, and STS-1 modes, do not allow OFSEL to float.
Instead, hardwire the highest resistor value and switch in series or parallel resistors as
needed. Example: For a DS3/E3 application, hardwire 5.23kΩ for DS3 and switch in
series 1.58kΩ to get 6.81kΩ for E3.
T3/E3/STS-1 Select. TESS determines the mode of operation for the device.
0 = E3
1 = T3 (DS3)
Float = STS-1
(Table
Figure 1-6
2-B). If EFE = 0, TDS0 is ignored.
18 of 27
and
Figure 1-7
FUNCTION
3
are met. See Section
(Table
(Table
for more details. If EFE = 0, the PRBS pin
(Figure
2-B). If EFE = 0, TDS1 is ignored. If
2-C).
1-2).
1.3
for additional details