ISL12026 Intersil Corporation, ISL12026 Datasheet
ISL12026
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ISL12026 Summary of contents
Page 1
... Data Sheet Real Time Clock/Calendar with EEPROM The ISL12026 device is a micro power real time clock with timing and crystal compensation, clock/calender, power-fail indicator, two periodic or polled alarms, intelligent battery backup switching, and integrated 512 x 8bit EEPROM configured in 16 Byte per page. ...
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... The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated This input provides a backup supply voltage to the device. V BAT that the Power Supply ISL12026 OSC COMPENSATION TIMER FREQUENCY 1Hz OSCILLATOR CALENDAR DIVIDER LOGIC STATUS CONTROL/ REGISTERS REGISTERS ...
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... Output Low Voltage OL I Output Leakage Current LO EEPROM Specifications SYMBOL PARAMETER EEPROM Endurance EEPROM Retention 3 ISL12026 Thermal Information OUT Pins Thermal Resistance (Note SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Lead Temperature (Soldering, 10s 300°C = +2.7V to +5.5V 3.3V ...
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... Input Data Hold Time HD:DAT t STOP Condition Setup Time SU:STO t STOP Condition Hold Time for HD:STO Read, or Volatile Only Write t Output Data Hold Time DH Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip. 4 ISL12026 TEST CONDITIONS MIN -0 4mA 5. 5.5V ...
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... Write operation, to the end of the self-timed internal non-volatile write cycle. Timing Diagrams Bus Timing SCL t SU:STA t HD:STA SDA (INPUT TIMING) SDA (OUTPUT TIMING) Write Cycle Timing SCL SDA 8TH BIT OF LAST BYTE 5 ISL12026 TEST CONDITIONS = 400kHz specification must be followed HIGH LOW t SU:DAT t HD:DAT ACK STOP ...
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... V BAT BAT, 5.00 4.50 Vdd=5.5V 4.00 3.50 Vdd=3.3V 3.00 2.50 2.00 1.50 1.00 0.50 0.00 -45 -35 -25 - Temperature FIGURE TEMPERATURE DD3 4.50 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 1.8 2.3 2.8 3.3 3.8 Vdd (V) FIGURE DD3 6 ISL12026 Temperature is 25°C unless otherwise specified 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 4.3 4.8 5.3 SBIB = 0 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0. -20 -40 4.3 4.8 5.3 -32 -28 -24 -20 -16 -12 DD SCL,SDA pullups = 0V BSW = 1.80 2.30 2.80 3.30 3 ...
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... X1, X2 The X1 and X2 pins are the input and output, respectively inverting amplifier. An external 32.768kHz quartz crystal is used with the ISL12026 to supply a timebase for the real time clock. Internal compensation circuitry provides high pin accuracy over the operating temperature range from BAT -40° ...
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... CCR. Prior to writing to the CCR (except the status register), however, the WEL and RWEL bits must be set using a three 8 ISL12026 step process (See section “Writing to the Clock/Control Registers.”) The CCR is divided into 5 sections. These are: 1. Alarm 0 (8 bytes ...
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... RTCF: Real Time Clock Fail Bit - Volatile This bit is set to a “1” after a total power failure. This is a read only bit that is set by hardware (ISL12026 internally) when the device powers up after having lost all power to the device (both V DD whether V the supplies does not set the RTCF bit to “ ...
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... RTC registers. As the RTC advances, the alarm will be triggered once a match occurs between the alarm registers and the RTC registers. Any one alarm register, multiple registers, or all registers can be 10 ISL12026 TABLE 2. CLOCK/CONTROL MEMORY MAP BIT ...
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... ISL12026 Oscillator Compensation Registers There are two trimming options. ARRAY LOCK - ATR. Analog Trimming Register None - DTR. Digital Trimming Register Upper 1/4 These registers are non-volatile. The combination of analog Upper 1/2 and digital trimming can give up to -64 to +110 ppm of total adjustment ...
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... Writing to the Clock/Control Registers Changing any of the bits of the clock/control registers requires the following steps: 12 ISL12026 1. Write a 02h to the Status Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceded by a start and ended with a stop) ...
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... V DD TRIP ≈ 2.2V where V TRIP • Battery Backup Mode ( Normal Mode (V BAT 13 ISL12026 The ISL12026ISL12026 device will switch from the V V mode when one of the following conditions occurs: OUT DD - Condition 1: V where V - Condition 2: V where V There are two discrete situations that are possible when ...
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... Figure 13). SCL SDA SCL SDA 14 ISL12026 mode when the Stop Condition DD All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence ...
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... ISL12026 1 START After loading the entire Slave Address Byte from the SDA bus, the ISL12026 compares the device identifier and device select bits with ‘1010111’ or ‘1101111’. Upon a correct compare, the device outputs an acknowledge on the SDA line. Following the Slave Byte is a two byte word address. The word address is either supplied by the master device or obtained from an internal counter ...
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... ISL12026 will not initiate an internal write cycle, and will continue to ACK commands. Page Write The ISL12026 has a page write operation initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is ...
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... To do this, the master issues a start condition followed by the Memory Array Slave Address Byte for a write or read operation (AEh or AFh). If the ISL12026 is still busy with the non-volatile write cycle then no ACK will be returned. When the ISL12026 has completed the write operation, an ACK is returned and the host can proceed with the read or write operation ...
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... In a similar operation called “Set Current Address,” the device sets the address if a stop is issued instead of the second start shown in Figure 21. The ISL12026 then goes into standby mode after the stop and all bus activity will be ignored until a start is detected. This operation loads the new address into the address counter ...
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... TABLE 6. CRYSTAL PARAMETERS REQUIRED FOR INTERSIL RTCs PARAMETER Frequency Frequency Tolerance Turnover Temperature Operating Temperature Range Parallel Load Capacitance Equivalent Series Resistance 19 ISL12026 DATA DATA K (1) (2) FIGURE 22 ...
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... RTC. Care needs to be taken in layout of the RTC circuit to avoid noise pickup. Below in Figure suggested layout for the ISL12026 or ISL12027 devices in 8 pin SO package. FIGURE 23. SUGGESTED LAYOUT FOR INTERSIL RTC IN SO-8 20 ISL12026 TABLE 7 ...
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... OUT oscilloscope (after enabling it with the control register, and using a pull-up resistor for an open-drain output). Alternatively, the ISL12026 device has an IRQ/F which can be checked by setting an alarm for each minute. Using the pulse interrupt mode setting, the once-per-minute interrupt functions as an indication of proper oscillation. ...
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... If the microcontroller and bus pullups are also powered by the battery, then the ISL12026 can communicate in battery backup mode. This mode places the ISL12026 device in the same operating mode as the X1226 legacy device. • Mode C - This mode combines Standard mode battery ...
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... The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 23 ISL12026 M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE M B ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 24 ISL12026 M8.173 8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE M ...