HD44780U Hitachi Semiconductor (acquired by Renesas), HD44780U Datasheet - Page 22

• Manufacturer Part Number: HD44780U
• Description: Dot Matrix Liquid Crystal Display Controller/driver
• Manufacturer: Hitachi Semiconductor (acquired by Renesas)

HD44780U
Timing Generation Circuit
The timing generation circuit generates timing signals for the operation of internal circuits such as
DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU
access are generated separately to avoid interfering with each other. Therefore, when writing data to
DDRAM, for example, there will be no undesirable interferences, such as flickering, in areas other than
the display area.
Liquid Crystal Display Driver Circuit
The liquid crystal display driver circuit consists of 16 common signal drivers and 40 segment signal
drivers. When the character font and number of lines are selected by a program, the required common
signal drivers automatically output drive waveforms, while the other common signal drivers continue to
output non-selection waveforms.
Sending serial data always starts at the display data character pattern corresponding to the last address of
the display data RAM (DDRAM).
Since serial data is latched when the display data character pattern corresponding to the starting address
enters the internal shift register, the HD44780U drives from the head display.
Cursor/Blink Control Circuit
The cursor/blink control circuit generates the cursor or character blinking. The cursor or the blinking will
appear with the digit located at the display data RAM (DDRAM) address set in the address counter (AC).
For example (Figure 8), when the address counter is 08H, the cursor position is displayed at DDRAM
address 08H.
188
Note: The cursor or blinking appears when the address counter (AC) selects the character
For a 1-line display
For a 2-line display
generator RAM (CGRAM). However, the cursor and blinking become meaningless.
The cursor or blinking is displayed in the meaningless position when the AC is a CGRAM address.
Display position
DDRAM address
(hexadecimal)
Display position
DDRAM address
(hexadecimal)
Figure 8 Cursor/Blink Display Example
AC
AC6
00
00
40
0
1
1
AC5
01
01
41
0
2
2
AC4
02
02
42
0
3
3
AC3
03
03
43
1
4
4
AC2
04
04
44
0
5
5
AC1
05
05
45
0
6
6
AC0
06
06
46
0
7
7
cursor position
cursor position
07
07
47
8
8
08
08
48
9
9
10
09
10
09
49
0A
0A
4A
11
11